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A modeling approach for power integrity simulation in 3D-IC designs
Vinayakam Subramanian and Jairam Sukumar
4/27/2012 10:10 AM EDT
A modeling approach
There are various reasons for using an on-chip power grid model. First, in order to reduce computational complexity, the model can be deployed for hierarchical analysis of on-chip power networks. Second, this approach includes integrated board-level analysis requirements involving third-party SoCs. As an extension of this model, the same approach can be used for integrating 3D power grid systems. Chip model accuracy is a critical metric to validate effectiveness, and to define clear validation criteria for qualifying the model’s accuracy. Accuracy constraints in 3D power grid analysis are more stringent compared to board-level analysis because timing closure targets are decided based on the IR drop budgets of individual SoCs. Basic requirements for a first order circuit model to emulate a SoC power grid include capturing the current signatures at the power ports and its associated power network. Assuming this model is an N-port network, it equates the current signature and the equivalent passive network of the power grid at the SoC port.
The current signature is a direct consequence of the application profile, so the application scenario pertaining to analysis is profiled in a RTL/gate-level logic simulator. This simulation stamp is subjected to a cycle-by-cycle power analysis of the design. A worst case power cycle is selected, and for an entire cycle the transient power grid analysis is performed. This approach comprehends the transient analysis requirements. The modeling requirement for a static analysis is a much simpler subset. For 3D modeling requirements, interface ports must be defined at the silicon boundary and not at the package boundary. The switching frequency content of the logic circuit is a key parameter that will decide the complexity of the model order reduction for the SoC power grid. Since frequency response accuracy is desired in this model, frequency domain-based order methods are used for model creation. The model also complies for passivity and stability after order reduction, and is scalable with respect to power grid hierarchy. To reduce the complexity of computation by abstracting multiple power ports into one, the equivalent parasitic network and the current signatures scale accordingly. Expanding the chip power model to represent a SoC in its entirety is also possible.
This is essentially a two-step approach. A stand-alone computation is performed first, to create the chip power model of the SoC being integrated. Second, a model is included along with the external circuit-level components of the base SoC, for which the IR analysis must be performed. The external circuit-level components include the package and the board-level circuit parameters connected to the 3D system. The integration approach is illustrated here with one stacked die represented by a chip power model. The dashed line enclosure around the top die indicates it can be abstracted as a chip power model and integrated to the base die for an analysis computation.
Static analysis
In a concurrent static IR simulation, layouts for both die are included in the set-up and a combined static analysis is performed for the integrated 3D system. In a model-based static IR simulation, a chip power model is created for the top die and then integrated into the 3D framework for static IR analysis. Static analysis results are compared between the concurrent and model-based approaches. The error margin between the two types of analysis provides a perspective of the model’s accuracy. The figures show the IR drop map obtained through concurrent and model-based analysis. The worst case IR drop for the bottom die is exactly the same for the two approaches – validating the chip power model. Along with the IR drop map, cell instances with worst case IR drop are monitored for the base SoC. The top ten instances with maximum IR drop are exactly the same between the two approaches, confirming the model accuracy for static IR analysis.
Dynamic analysis
Dynamic analysis results are analysed for both concurrent and model-based approaches. A chip power model is created of the top SoC for dynamic analysis mode, and analysis is performed by the model and concurrent based approaches. The following figures illustrate cell distribution of worst case IR drop in both the model-based and concurrent analysis. The distribution is plotted for the base SoC and a model-based analysis is performed, showing the distribution profile is similar between the two approaches. The order of magnitude difference between the cell counts can be attributed to the fact that in the model-based approach, there are no cell counts being accounted for the top die, but they are comprehended for a concurrent analysis. Worst case IR drop violating instances computed between the two approaches and the top 20 cell instances all match, but they are not necessarily in the same order. This again demonstrates the accuracy of the model-based approach for dynamic IR analysis.
Chip Power Model Analysis: Concurrent Analysis:
IR Histogram IR Histogram
An order of magnitude reduction in runtime for model-based analysis is shown in the example. While concurrent analysis can take 45 minutes of elapsed time to execute, a model-based analysis is complete within 10 minutes of elapsed time.
Apart from validating a modeling approach, analysis can also yield various insights into the power grid design. The concurrent dynamic analysis shows the top die has a higher IR drop compared to the bottom die, as power is supplied through a TSV. This also helps validate the sufficiency of power TSV structures for power distribution.
So in conclusion, using a modeling approach with an existing chip power model for package co-design analysis in a 3D-IC chip model-based voltage drop analysis, we have seen that a chip power model is accurate for both static and dynamic analysis, vis-a-vis concurrent analysis, and learned how concurrent and model-based approaches deliver both accuracy and computation time.
Vinayakam Subramanian is a lead applications engineer at Apache Design, Inc. (a subsidiary of ANSYS). He has over five years of experience in the electronic design automation (EDA) industry with a focus on system-on-chip (SoC) level full-chip power integrity simulation and chip-package-system (CPS) co-analysis methodology definitions for both power and signal integrity analysis.
Jairam Sukumar received his B.S. in Electrical Engineering from Dayalbagh, Agra and Masters in Electronics Design from the Indian Institute of Science, Bangalore, in 1998 and 2000, respectively. Currently he is a Member of Technical Staff at Texas Instruments, Bangalore. Previously at TI he lead the Physical Design of Mixed Signal SoCs for Broadband Applications. His current focus is the development of methodologies for power estimation, and optimization of SoCs and electrical and reliability analysis. He is a senior member of the IEEE.
This posting is part of the EDA Designline power series and is archived and updated. The root is accessible here. Please send me any updates, additions, references, white papers or other materials that should be associated with this posting. Thank you for making this a success - Brian Bailey.
There are various reasons for using an on-chip power grid model. First, in order to reduce computational complexity, the model can be deployed for hierarchical analysis of on-chip power networks. Second, this approach includes integrated board-level analysis requirements involving third-party SoCs. As an extension of this model, the same approach can be used for integrating 3D power grid systems. Chip model accuracy is a critical metric to validate effectiveness, and to define clear validation criteria for qualifying the model’s accuracy. Accuracy constraints in 3D power grid analysis are more stringent compared to board-level analysis because timing closure targets are decided based on the IR drop budgets of individual SoCs. Basic requirements for a first order circuit model to emulate a SoC power grid include capturing the current signatures at the power ports and its associated power network. Assuming this model is an N-port network, it equates the current signature and the equivalent passive network of the power grid at the SoC port.
The current signature is a direct consequence of the application profile, so the application scenario pertaining to analysis is profiled in a RTL/gate-level logic simulator. This simulation stamp is subjected to a cycle-by-cycle power analysis of the design. A worst case power cycle is selected, and for an entire cycle the transient power grid analysis is performed. This approach comprehends the transient analysis requirements. The modeling requirement for a static analysis is a much simpler subset. For 3D modeling requirements, interface ports must be defined at the silicon boundary and not at the package boundary. The switching frequency content of the logic circuit is a key parameter that will decide the complexity of the model order reduction for the SoC power grid. Since frequency response accuracy is desired in this model, frequency domain-based order methods are used for model creation. The model also complies for passivity and stability after order reduction, and is scalable with respect to power grid hierarchy. To reduce the complexity of computation by abstracting multiple power ports into one, the equivalent parasitic network and the current signatures scale accordingly. Expanding the chip power model to represent a SoC in its entirety is also possible.
This is essentially a two-step approach. A stand-alone computation is performed first, to create the chip power model of the SoC being integrated. Second, a model is included along with the external circuit-level components of the base SoC, for which the IR analysis must be performed. The external circuit-level components include the package and the board-level circuit parameters connected to the 3D system. The integration approach is illustrated here with one stacked die represented by a chip power model. The dashed line enclosure around the top die indicates it can be abstracted as a chip power model and integrated to the base die for an analysis computation.
Two-Die CPM Integration Set-up
Static analysis
In a concurrent static IR simulation, layouts for both die are included in the set-up and a combined static analysis is performed for the integrated 3D system. In a model-based static IR simulation, a chip power model is created for the top die and then integrated into the 3D framework for static IR analysis. Static analysis results are compared between the concurrent and model-based approaches. The error margin between the two types of analysis provides a perspective of the model’s accuracy. The figures show the IR drop map obtained through concurrent and model-based analysis. The worst case IR drop for the bottom die is exactly the same for the two approaches – validating the chip power model. Along with the IR drop map, cell instances with worst case IR drop are monitored for the base SoC. The top ten instances with maximum IR drop are exactly the same between the two approaches, confirming the model accuracy for static IR analysis.
Concurrent Static IR Analysis
Chip Power Model Static IR Analysis
Dynamic analysis
Dynamic analysis results are analysed for both concurrent and model-based approaches. A chip power model is created of the top SoC for dynamic analysis mode, and analysis is performed by the model and concurrent based approaches. The following figures illustrate cell distribution of worst case IR drop in both the model-based and concurrent analysis. The distribution is plotted for the base SoC and a model-based analysis is performed, showing the distribution profile is similar between the two approaches. The order of magnitude difference between the cell counts can be attributed to the fact that in the model-based approach, there are no cell counts being accounted for the top die, but they are comprehended for a concurrent analysis. Worst case IR drop violating instances computed between the two approaches and the top 20 cell instances all match, but they are not necessarily in the same order. This again demonstrates the accuracy of the model-based approach for dynamic IR analysis.
Chip Power Model Analysis: Concurrent Analysis:
IR Histogram IR Histogram
An order of magnitude reduction in runtime for model-based analysis is shown in the example. While concurrent analysis can take 45 minutes of elapsed time to execute, a model-based analysis is complete within 10 minutes of elapsed time.
Apart from validating a modeling approach, analysis can also yield various insights into the power grid design. The concurrent dynamic analysis shows the top die has a higher IR drop compared to the bottom die, as power is supplied through a TSV. This also helps validate the sufficiency of power TSV structures for power distribution.
So in conclusion, using a modeling approach with an existing chip power model for package co-design analysis in a 3D-IC chip model-based voltage drop analysis, we have seen that a chip power model is accurate for both static and dynamic analysis, vis-a-vis concurrent analysis, and learned how concurrent and model-based approaches deliver both accuracy and computation time.
Vinayakam Subramanian is a lead applications engineer at Apache Design, Inc. (a subsidiary of ANSYS). He has over five years of experience in the electronic design automation (EDA) industry with a focus on system-on-chip (SoC) level full-chip power integrity simulation and chip-package-system (CPS) co-analysis methodology definitions for both power and signal integrity analysis.Jairam Sukumar received his B.S. in Electrical Engineering from Dayalbagh, Agra and Masters in Electronics Design from the Indian Institute of Science, Bangalore, in 1998 and 2000, respectively. Currently he is a Member of Technical Staff at Texas Instruments, Bangalore. Previously at TI he lead the Physical Design of Mixed Signal SoCs for Broadband Applications. His current focus is the development of methodologies for power estimation, and optimization of SoCs and electrical and reliability analysis. He is a senior member of the IEEE.This posting is part of the EDA Designline power series and is archived and updated. The root is accessible here. Please send me any updates, additions, references, white papers or other materials that should be associated with this posting. Thank you for making this a success - Brian Bailey.
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