Three Dimensional Integrated Circuits (3DIC) are generating increased interest as a way to increase speed and density while reducing power and form factor. System level integration in Package (SiP) has joined “System on Chip (SoC)” as one of the primary mechanisms to drive the electronic industry. Quotes such as “Smartphones and Tablets will increasingly owe their prowess to better chip packaging” [Apte11] are now common, and consortia such as the International Technology Roadmap for Semiconductors [ITRS09], SEMI [3DS‐IC], Si2 [Open3D], JEDEC [3D‐ICs] have all established committees or focus areas on 3DIC. The challenges to develop 3DIC technologies however are formidable, encompassing supply chains, manufacturing, standardization and design technology.
This paper focuses on a fundamental aspect of design technology for 3DICs: Understanding the electromagnetic behavior of 3D structures and how to model them in practice. It examines novel electromagnetic modeling aspects of 3DICs, in particular the use of silicon substrates such as silicon interposer, redistribution layer (RDL) and Through Silicon Via (TSV). It shows how to model electromagnetic properties of silicon substrates, RDL and TSV, how to capture the physical effects in a full 3D solver, and how to incorporate these models into electromagnetic simulation tools. The paper concludes with some examples that illustrate the techniques we have developed.
Three‐Dimensional Integration Roadmap
Recent announcements such as Xilinx’ Virtex®‐7 200T FPGA and TSMC’s Reference Flow 11.0 show the use of stacked silicon integration technology based on silicon interposers with TSV in production. The use of such techniques is expected to increase dramatically in the near future, posing interesting technical challenges. The ITRS Roadmap for Assembly and Packaging [ITRS09] states that “Modeling of 3D structures”, “Through Silicon Vias (TSV)” and “3D tools for System in Package (SiP)” are among the difficult challenges for the decade to come. Multiple 3D techniques are being developed, driven by the necessity of higher densities, shorter interconnects and lower power. Examples include mounting ICs on a Silicon Interposer, Stacked Dies and Package on Package (PoP). Through Silicon Vias (TSVs) are used to connect the different levels in several of these technologies:
- Coarse TSV are used for die‐to‐ball interconnection, such as in Wafer‐Level Packaging. Coarse TSV have a pitch of the order of 100μm which is expected to decrease to about 40μm by 2020
- Fine TSV are used for die to die interconnect and have a pitch of several micrometers, projected to be as low as 2μm by 2020
Advanced substrates, silicon interposers and redistribution layers all have feature dimensions in the micrometer range, as small as 10μm and as large as several hundreds of micrometers and they are not expected to shrink by more than perhaps by a factor of two in this decade. These 3D structures are large compared to on‐chip dimensions and need to be modeled electromagnetically to take into account inductance and high‐frequency effects. In addition, silicon resistivity, loss and capacitance (potentially depletion capacitance in silicon) need to be modeled.