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Dr DSP
Great examples! I didn't consider how DFT would be impacted by power ...
Power awareness in RTL design analysis
Narayana Koduri
7/23/2012 11:32 AM EDT
Power-intent aware DFT analysis
It’s very important to ensure that circuits are correctly designed for manufacturing test. The correct insertion of design for test logic (DFT) helps effective operation of ATPG tools to generate test patterns for high test quality. Let us take the same circuit in Figure 1, we discussed for CDC analysis. In this circuit, if the register “EN” has been changed to a scan flip-flop by synthesis, then during scan shift mode, the isolation enable signal value can change from 1->0. This will isolate the power domain outputs but the logic at register “S” cannot be testable. The same issue is also applicable to power switch control signals as well as retention control logic. So, an additional test circuit needs to be added for low power cells such as isolation, retention and power switches. Hence, it’s very critical to perform power aware DFT analysis during the early design stages, preferably at RTL.
Power-intent aware timing analysis
In figure 2, the power intent is captured in CPF which defines multiple voltage domains Vtop, V1 operating at 0.8 Volts and 0.6 Volts respectively. To meet the timing in the V1 domain, the cells in the critical path need to have higher drive strength or additional buffers need to be added for timing optimization. However, if timing analysis is performed without the awareness of power, then timing will not be met and may need many synthesis iterations. So, it’s essential to perform power aware timing analysis for multi-voltage designs. This is not only useful for timing but also impacts area as higher drive strength cells have higher area.
Another important aspect to be considered is physical placement of voltage domains in the design, where blocks/logic operating at similar voltages need to be placed near to each other. This helps to avoid congestion of power/ground nets that need to be routed based on physical placement of blocks/logic.
Power intent awareness also plays a vital role in RTL power optimization. Let us consider the circuit in figure 3. In this design, we have a power management control unit (PMU), and two blocks “blk1” and “blk2”. Logic transfer occurs between the switch domain (blk1) and always-on domain (blk2). In this case, data is fed from the upstream register (S) to the downstream register (D). During synthesis, isolation logic will be inserted to propagate the known logic at the switched off domain output. However, clock is still being fed to downstream register (D) which means data at the input of downstream (D) is stable due to the control signal that switches off the power domain. So, RTL power optimization tools are aware of the power intent that is defined in UPF/CPF, it can derive this stability condition and use this for gating the clock of downstream register (D), resulting in power savings.
Power-intent aware RTL power estimation
Power intent awareness is mandatory for early estimating power with multiple voltage islands and power islands. RTL power tools must consider switch off conditions as well as operating voltages of different islands for accurate power estimation. There is also other critical information that can be leveraged to estimate the power of additional structures that get added during implementation. RTL power estimation tools cannot only account for the additional area/leakage due to low power cells such as level shifters, isolation logic, retention cells, cells with bias capability or power switch cells, but also their impact on dynamic power.
Summary
In conclusion, we have illustrated scenarios where power intent awareness plays a critical role in verification and analysis of different aspects of the RTL design. Atrenta’s SpyGlass platform provides solutions for early power intent verification at RTL, post synthesis and post layout stages and supports both the CPF and UPF formats. These solutions can be used to validate the design for not only power intent but also the impact of power management logic on CDC or DFT early at RTL to ensure successful handoff for downstream implementation.
About the author
Narayana Koduri is a senior staff applications engineer for the SpyGlass Power product line at Atrenta Inc. and has been supporting semiconductor designers in the areas of RTL power estimation, reduction and verification for the past 8 years. He has 11 years of experience in EDA and chip design. Prior to joining Atrenta, he held an application/design engineer position at Trident Tech Labs, India. Narayana holds a bachelor degree in engineering from Anna University, India.
If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you).
It’s very important to ensure that circuits are correctly designed for manufacturing test. The correct insertion of design for test logic (DFT) helps effective operation of ATPG tools to generate test patterns for high test quality. Let us take the same circuit in Figure 1, we discussed for CDC analysis. In this circuit, if the register “EN” has been changed to a scan flip-flop by synthesis, then during scan shift mode, the isolation enable signal value can change from 1->0. This will isolate the power domain outputs but the logic at register “S” cannot be testable. The same issue is also applicable to power switch control signals as well as retention control logic. So, an additional test circuit needs to be added for low power cells such as isolation, retention and power switches. Hence, it’s very critical to perform power aware DFT analysis during the early design stages, preferably at RTL.
Power-intent aware timing analysis
In figure 2, the power intent is captured in CPF which defines multiple voltage domains Vtop, V1 operating at 0.8 Volts and 0.6 Volts respectively. To meet the timing in the V1 domain, the cells in the critical path need to have higher drive strength or additional buffers need to be added for timing optimization. However, if timing analysis is performed without the awareness of power, then timing will not be met and may need many synthesis iterations. So, it’s essential to perform power aware timing analysis for multi-voltage designs. This is not only useful for timing but also impacts area as higher drive strength cells have higher area.
Another important aspect to be considered is physical placement of voltage domains in the design, where blocks/logic operating at similar voltages need to be placed near to each other. This helps to avoid congestion of power/ground nets that need to be routed based on physical placement of blocks/logic.
Figure 2: CPF example for synthesis and physical design implementation
Power-intent aware RTL power optimizationPower intent awareness also plays a vital role in RTL power optimization. Let us consider the circuit in figure 3. In this design, we have a power management control unit (PMU), and two blocks “blk1” and “blk2”. Logic transfer occurs between the switch domain (blk1) and always-on domain (blk2). In this case, data is fed from the upstream register (S) to the downstream register (D). During synthesis, isolation logic will be inserted to propagate the known logic at the switched off domain output. However, clock is still being fed to downstream register (D) which means data at the input of downstream (D) is stable due to the control signal that switches off the power domain. So, RTL power optimization tools are aware of the power intent that is defined in UPF/CPF, it can derive this stability condition and use this for gating the clock of downstream register (D), resulting in power savings.
Figure 3: Power optimization by shutting clock across domains
Power-intent aware RTL power estimation
Power intent awareness is mandatory for early estimating power with multiple voltage islands and power islands. RTL power tools must consider switch off conditions as well as operating voltages of different islands for accurate power estimation. There is also other critical information that can be leveraged to estimate the power of additional structures that get added during implementation. RTL power estimation tools cannot only account for the additional area/leakage due to low power cells such as level shifters, isolation logic, retention cells, cells with bias capability or power switch cells, but also their impact on dynamic power.
Summary
In conclusion, we have illustrated scenarios where power intent awareness plays a critical role in verification and analysis of different aspects of the RTL design. Atrenta’s SpyGlass platform provides solutions for early power intent verification at RTL, post synthesis and post layout stages and supports both the CPF and UPF formats. These solutions can be used to validate the design for not only power intent but also the impact of power management logic on CDC or DFT early at RTL to ensure successful handoff for downstream implementation.
About the author
Narayana Koduri is a senior staff applications engineer for the SpyGlass Power product line at Atrenta Inc. and has been supporting semiconductor designers in the areas of RTL power estimation, reduction and verification for the past 8 years. He has 11 years of experience in EDA and chip design. Prior to joining Atrenta, he held an application/design engineer position at Trident Tech Labs, India. Narayana holds a bachelor degree in engineering from Anna University, India.
If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you).
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Dr DSP
7/24/2012 2:22 PM EDT
Great examples! I didn't consider how DFT would be impacted by power constraints. Really an eye opener.
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