Power noise reduction by optimizing the dynamic power signature of digital ICs

Analyzing the package chip model

Package-level dynamic voltage drop is often dominated by L-noise, as indicated by v = L di/dt. This means that reducing current demand peaks is not enough to handle PNI challenges. Transient current slopes (di/dt) must also be effectively dealt with. High frequency power noise must be decreased. Not surprisingly, it is seen in Figures 2 and 3 how the voltage drop across the package constitutes a higher degree of the total dynamic voltage drop (peak drop) in a high-inductance package compared to a low-inductance package. It is also seen how the on-chip part of the voltage drop is somewhat smaller in the high-inductance package. This is due to the high package inductance filtering the high frequency content of the power noise, thus not exposing the on-chip resistive network to this.

Figures 3 and 4 compare a design in a low-inductance package with a low (0.8 nF) and high (1.4 nF) level of on-chip decap respectively. It is seen how the added decap reduces the dynamic voltage drop peak as expected. An interesting observation is that in order to achieve an acceptable peak level of less than 15% dynamic voltage drop, a full 1.4 nF of decap is required in the non-power shaped version of the design. To reach that same level in the power shape optimized version of the same design, only 0.8 nF of total decap (43% less) is required. Much of this decap is intrinsically present in non-switching logic cells, and the percentage reduction in explicitly added decap is an even higher number. As such, when applying power shape optimization it is possible to make do with significantly less decap, within a given power noise budget.
Another observation is that the high frequency content of the power noise, seen clearly in both Figures 3 and 4 as the sharp voltage drop spikes across the package, is effectively eliminated by power shaping. High frequency power noise is an indication that logic cells are being starved of their immediate power requirement. The high-frequency content of the power demand is often difficult to accommodate due to the inductive power tracing, e.g. in the package. To make things worse, the effectiveness of on-chip decaps drops in the high frequency range, due to the series resistance of the decap device. Decaps further more work best locally due to resistance in the on-chip power grid. Their effectiveness, especially in the high-frequency range, drops with the distance to the source of the current demand. Finally, the effectiveness of decaps decreases considerably with scaling process nodes, as the intrinsic capacitance is going down, while the effective series resistance is going up [2].
 
The benefit of power shaping on the high-frequency content of the voltage drop is also seen by looking at the slopes of the voltage waveforms. The RC-network of the on-chip PDN works as a low-pass filter, smoothing the slopes. Power shaping is fully complementary to the passive filtering effect of the on-chip PDN. It simply reduces the high-frequency content of the noise instigator, the current demand of the cells. It is seen in all Figures 2 to 4 how power shaping has a significant effect on the slopes, on top of the low-pass effect of the decaps.

In conclusion of these observations, it is clear that the biggest hurdle to achieving PNI at advanced process nodes lies in handling high frequency power demand. To address high-frequency PNI challenges, you need to work very closely to the source of the dynamic power drain: directly on the chip. A power shaping approach which changes the power noise profile of a design by optimizing the current demand waveform, Icell of Figure 1, works orthogonally to approaches directed at PDN implementation itself, the R’s, C’s and L’s of Figure 1. Power shaping works particularly well in the high-frequency range, where traditional physical-level approaches are at a lack [3].

Dynamic Power Shaping, as enabled by Teklatech’s FloorDirector tool, constitutes a viable path towards PNI optimization in advanced SoC designs. It works complementary to existing PDN optimization techniques. It provides a solution to high-frequency power noise challenges that cannot be addressed effectively today, challenges which are increasingly problematic at scaling technology nodes.

References
[1] Ludovic Larzul, "Power-aware emulation tests power islands", EE Times, 2012.
[2] Aveek Sarkar, “Power delivery network design requires chip-package-system co-design approach”, EE Times, 2010.
[3] Fabio Campi, Davide Pandini, Tobias Bjerregaard, Mikkel Stensgaard, “A Power Shaping Methodology for Supply Noise and EMI Reduction”, Design Automation Conference User Track, 2010.

About the author
Tobias Bjerregaard is CEO and Founder of Teklatech. He has spent more than a decade with a focus on leading-edge micro-electronics, both in an industrial, commercial, and research capacity. He has invented and patented semiconductor technology innovations in the areas of power integrity, clock distribution, and on-chip communication networks. Through his leadership, Teklatech has developed and commercialized multiple generations of ground-breaking power and noise integrity optimization EDA technologies. Dr. Bjerregaard has received numerous prestigious accolades for his individual achievements, has written a range of papers for leading industry publications and has worldwide recognition for his work. He holds MS.EE. and Ph.D. degrees in micro-electronics, from the Technical University of Denmark.

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