Ticket execution environment
preparing library files and design data, members of the project team
can take tickets for design steps, such as Synthesis, LEC, CTS, or STA
from a Ticket Data Base. The ticket file is a task description file (See
Figure 11) that contains the following information:
- Where is the input and output data
- What to do with predefined flow
- Associated flow parameters to execute the task
The WFM system reads the above information and creates an EDA tool
execution environment. It actually generates a make file based execution
environment that automatically handles job dependency. WFM will record
the job running environment and setting, so designers can easily track
their jobs result and source data. WFM system can link with a Sun Grid
Engine for job queuing control, but it can be easily ported to any other
job queue system like LSF. Users can use WFM Job Manager to execute and
monitor design jobs. WFM Job Manager is a GUI that visualizes the job
dependency, control job execution and monitor job status (Figure 12).
Figure 11: WFM Ticket File Example
Figure 12: WFM Ticket Execution and Job Manager
Quality control factor
each design stage, designers have to look for several quality checking
items in the tool report. WFM provides a quality control mechanism that
systematically monitors the design quality. After executing each step,
WFM automatically extracts quality control factors (QCF) from EDA tool
reports and log files. The QCFs are defined in WFM flow definition
package and includes such items as the number of floating pin, the
number of slack violation path, and other similar details.
WFM also provides graphic user interfaces. The WFM Data Manager can
analyze design quality, summarize the quality control factors .and then
highlight the job stage version with a circle mark. If the tool result
needs to be debugged, WFM will highlight the job stage version with a
red circle mark. If there is something else that needs to be check, the
job stage will be marked with a yellow circle. This way, users can
quickly review the design quality (Figure 13). WFM automatically
transfers design data to other geographic regions, so the project leader
can easily review the quality of job stage versions implemented by the
other regions’ engineers.
Figure 13: WFM Data Manager Integrated with QCF Review Score Board
aggressive design schedules while ensuring the design quality, companies
should have a flow and data management system. The ideal system
integrates unified design data and library management, reusable flow
script package, EDA tool execution environment and quality control
factor extraction. The consistent working model helps cross-region
engineers smoothly collaborate to increase the design team's overall
productivity. Ultimately, the system helps designers avoid mistakes
caused by applying wrong data or settings.
One GUC project developed through it was a 40nm GPS chip. It
contains about 7 million equivalent logic gates. For multi mode multi
corner timing analysis, there were 5 function modes, 4 timing
environments, 5 RC corners, 3 setup-time and 13 hold-time library
signoff corners. In the past, designers had to prepare many scripts for
RC extraction, delay calculation, STA, and SI jobs, and they also had to
arrange the dependency relation between the job's data.
The WFM system automatically associated design data and constraint
files for each MMMC job and built their dependency graph (see Figure
14). Thus, designers could easily execute these jobs from the WFM GUI.
The project adopted WFM system to handle the timing signoff jobs and
completed them on schedule. It was a successful experience. In the first
year, there is only 20% of GUC's projects adopted this system. Now,
almost all projects adopt WFM. To date, GUC has taped out more than 70
designs that were run through the WFM system. The devices targeted a
number of manufacturing processes ranging from 28nm to 90 nm. The
systematic working model improved both project quality and schedule
Figure 14: MMMC Timing Signoff Job Dependency Graph
About the authors
Li is Global Unichip Corp.'s (GUC) Director, Design Service. He leads
the GUC’s design flow R&D team that develops the IC design
methodology for advanced technology nodes (40nm/28nm). Prior to joining
GUC, Albert worked for Cadence Design as the R&D Architect in the IC
Digital Design Group and has held other technical responsibilities with
Broadcom’s Network Switching Division, TSMC’s Design Service Division
and ISSI’s Nonvolatile Memory Division.
Lee is department manager of the Design Integration Management
Department at Global Unichip Corp.(GUC). He leads the GUC design flow
integration team that develops the design automation platform. Prior to
joining GUC, Reed worked at the National Chip Implementation Center on
R&D in the design flow development group.
Liu is manager of Global Unichip Corp.'s (GUC) Design Integration
Management Department. His team develops the design automation platform
for IC design. Previous to joining GUC, Louis worked at Dorado Design
Automation on R&D for the software development group.
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