Clock gating enable based integer dividers or Punch through dividers
Shown here is a simple implementation of a punch through clock divider.
Figure 4. Clock gating based dividers
Following is an illustration of waveform generation for Divide by 3 clock generation.
Figure 5. Waveform for divide by 3 clock generation
down counter is reinitialized once its count reaches zero from store
(N-1) register. The latch in the circuit ensures that enable generated
at the output of the NOR gate gets propagated to the AND gate only when
the clock is low. In absence of the latch the output clock might be not
be glitch free.
- RTL for clock
gating based dividers is fairly simple and additionally punch through
clocking scheme reduces DFT at-speed clocking complexity considerably.
- Some IPs, such as DDR, require 50% duty cycle which is not possible with punch through clocking.
timing paths that start from the rising edge of the clock and end with
the falling edge of the clock have to be met at ½ the clock in frequency
meaning that the STA team must check for such critical timing paths in
the design before finalizing on this clocking architecture.