Design Article
Tell us What You Think
We want to know what you thought about this Design. Let us know by adding a comment.
Configurable dividers for SOC / block-level clocking
Prateek Gupta, Priyanka Garg - Freescale
9/4/2012 9:08 AM EDT
Mux based dividers
A mux based divider implementation is shown below, followed by sample waveforms while performing a division by 3. Mux based dividers have clock flowing through the select pin of the 2:1 mux. The enable values at data pins of the mux toggle in accordance with the input clock in such a way that the logic generated at the output of the mux is exactly the desired clock output. There is one important catch in this type of implementation. Additional clock gating checks need to be added at the data inputs of the mux to ensure correct functionality of the clock divider circuitry. The timing checks have been shown in the waveforms.
Figure 6 mux based divider
Following waveforms are generated on dividing the input clock by 3.
Figure 7 waveforms for divide by 3
The timing check 1 is a half cycle setup check from the rising edge of the clock to the falling edge of the clock and hence can be very critical if the input clock is locked at very high frequency (for example PLL output is locked at very high frequencies to minimize jitter.)
RTL complexity is low and these are usually the designer’s choice for implementing 50% duty cycle clock dividers.
Advantages
A mux based divider implementation is shown below, followed by sample waveforms while performing a division by 3. Mux based dividers have clock flowing through the select pin of the 2:1 mux. The enable values at data pins of the mux toggle in accordance with the input clock in such a way that the logic generated at the output of the mux is exactly the desired clock output. There is one important catch in this type of implementation. Additional clock gating checks need to be added at the data inputs of the mux to ensure correct functionality of the clock divider circuitry. The timing checks have been shown in the waveforms.
Figure 6 mux based divider
Following waveforms are generated on dividing the input clock by 3.
Figure 7 waveforms for divide by 3
Figure 8. Timing checks
The timing check 1 is a half cycle setup check from the rising edge of the clock to the falling edge of the clock and hence can be very critical if the input clock is locked at very high frequency (for example PLL output is locked at very high frequencies to minimize jitter.)
RTL complexity is low and these are usually the designer’s choice for implementing 50% duty cycle clock dividers.
Advantages
- Integer division with 50% duty cycle and fractional division without 50% duty cycle
- Single source pin for all generated clocks (which is a Mux output).
- Additional Clock gating checks need to be deployed which can get timing critical
|
|
|
|
|
Navigate to related information