Synchronous clock domain crossings
Synchronous clock domain crossings
section describes various types of synchronous clock domain crossings.
Clocks which have a known phase and frequency relationship between them
are known as synchronous clocks. These are essentially the clocks
originating from the same clock-root. A clock crossing between such
clocks is known as a synchronous clock domain crossing. It can be
divided into several categories based on the phase and frequency
relationship of the source and destination clocks as follows:
- Clocks with the same frequency and zero phase difference
- Clocks with the same frequency and constant phase difference
- Clocks with different frequency and variable phase difference
- Integer multiple clocks
- Rational multiple clocks
the above sub categories may not be used in real designs but are being
considered here for completeness and better understanding of the
While describing all the above cases, it is assumed
that the source clock (C1) and the destination clock (C2) have the same
phase and frequency jitter and are balanced with the same specifications
of clock latency and skew. It is also assumed that the clocks begin
with a zero phase difference between them and the “clock to Q” delay of
the flops is 0.
Clocks with the same frequency and zero phase difference
refers to two identical clocks, as the clocks C1 and C2 have the same
frequency and 0 phase difference. Note, that as the clocks C1 and C2 are
identical and generated from the same root clock, the data transfer
from C1 to C2 is essentially not a clock domain crossing. For all
practical purposes, this is the case of a single clock design and is
considered here for completeness.
Whenever data is transferred
from clock C1 to C2, one complete clock cycle of C1 (or C2) is available
for data capture as shown in Figure 9.
Figure 9. Same frequency, same phase clocks
long as the combinational logic delay between the source and
destination flops is such that the setup and hold time of the circuit
can be met, the data will be transferred correctly. The only requirement
here is that the design should be STA (static timing analysis) clean.
In that case, there will be no problem of metastability, data loss or
Clocks with the same frequency and constant phase difference
are the clocks having the same time period but a constant phase
difference. A typical example is the use of a clock and its inverted
clock. Another example is a clock which is phase shifted from its parent
clock, for example by T/4 where T is the time period of the clocks.
See Figure 10. Clocks C1 and C2 have the same frequency but are phase shifted and C1 is leading C2 by 3T/4 time units.
Figure 10. Same frequency, phase shifted clocks
data is transferred from clock C1 to C2, there is more restriction on
the combinational logic delay due to smaller setup/hold margins. If the
logic delay at the crossing is such that the setup and hold time
requirements can be met, data will be transferred properly and there
will be no metastability. In all such cases, there is no need for a
synchronizer. The only requirement here is that the design should be STA
Clocks with different frequency and variable phase difference
are clocks which have a different frequency and a variable phase
difference. There can be two sub-categories here, one where the time
period of one clock is an integer multiple of the other and a second
where the time period of one clock is a non-integer (rational) multiple
of the other. In both cases, the phase difference between the active
edges of clocks is variable. These two cases are described in detail
Integer multiple clocks. In this case, the
frequency of one clock is an integer multiple of the other and the phase
difference between their active edges is variable. Here the minimum
possible phase difference between the active edges of 2 clocks would
always be equal to the time period of the fast clock.
example, see Figure 11. Here clock C1 is 3 times faster than clock C2.
Assuming T is the time period of clock C1, the time available for data
capture by clock C2 could be T, 2T or 3T depending on which edge of
clock C1 the data is launched. Hence, the worst case delay of any path
should meet the setup time with respect to the edge with a phase
difference of T. The worst case hold check would be made with respect to
the edge with 0 phase difference.
Figure 11. Integer multiple clocks
all such cases, one complete cycle of the faster clock is always
available for data capture, hence it should always be possible to meet
the setup and hold requirements. As a result there will be no
metastability or data incoherency and a synchronizer is not needed.
there can still be a problem of data loss in the case of fast to slow
clock crossing. (That is, the source clock is faster than the
destination clock.) In order to prevent this, the source data should be
held constant for at least one cycle of the destination clock. This can
be ensured by using some control circuit, for example, a simple finite
state machine (FSM) would work in this case. In the example shown in
Figure 11, if the source data is generated once in every 3 cycles of the
source clock, there would be no data loss.
For the case of slow to fast crossings, there will anyways be no data loss.
Rational multiple clocks.
In this case, the frequency of one clock is a rational or non-integer
multiple of the other clock and the phase difference between the active
clock edges is variable.
Unlike the situation where one clock is
an integer multiple of the other, here the minimum phase difference
between the two clocks can be very small- small enough to
cause metastability. Whether or not a metastability problem will occur
depends on the value of the rational multiple, and the design
technology. Three different cases are being considered here with the
help of examples.
In the first case, there is a sufficient phase
difference between the active edges of the source and destination
clocks such that there will be no metastability.
In the second
case, the active clock edges of the two clocks can come very close
together, close enough to cause metastability problem. However, in this
case the frequency multiple is such that, once the clock edges come
close together, there would be sufficient margin in the next cycle to
capture data properly without any setup or hold violation.
the third case, the clock edges of the two clocks can be close enough
for many consecutive cycles. This is similar to the behavior of
asynchronous clocks except that here the clock-root for both the clocks
is the same and hence the phase difference between the clocks can be
Note that in all the examples given below, some delay
values are used and it is assumed that a phase margin of less than or
equal to 1.5ns between the clock edges can cause metastability. This is
just a placeholder value and in real designs, it would be a function of
many things including technology used, flop characteristics, etc.
is the case when the active clock edges of both the clocks will never
come very close together, and in all cases there would be a sufficient
margin to meet the setup and hold requirements of the circuit.
a clock C from which 2 clocks C1 and C2 are derived with a frequency of
divide-by-3 and divide-by-2 respectively with respect to clock C. Here
clock C1 is 1.5 times slower than clock C2. As shown in Figure 12, the
time period of clock C1 is 15ns and of C2 is 10ns. The least possible
phase difference between the two clock edges is 2.5ns which should be
sufficient to meet setup and hold time requirements.
Figure 12. Clock edges never come very close together
additional combinational logic should not be added at the crossing due
to the very small setup/hold margins. If there is any logic, its delay
should meet the setup and hold time requirements. If this condition can
be met, there will be no metastability and no synchronizer would be
Further, if the crossing is a slow to fast crossing,
there will be no data loss. However, in case of a fast to slow clock
crossing, there can be data loss. In order to prevent this, the source
data needs to be held constant for at least one cycle of the destination
clock so that at least one active edge of the destination clock arrives
between two consecutive transitions on the source data.
this case, the active clock edges of both the clocks can come very
close together intermittently. In other words, the clock edges come
close together once and then there would be sufficient margin between
the edges for the next few cycles (to capture data properly) before they
come close again. Here the word “close” implies close enough to cause
In Figure 13, clocks C1 and C2 have time periods
10ns and 7ns respectively. Notice, that the minimum phase difference
between the two clocks is 0.5ns, which is very small. So, there are
chances of metastability and a synchronizer would be required.
to metastability, the data may not be captured in the destination
domain when the clock edges are very close together. However, in this
case, note that once the clock edges come very close together, in the
next cycle there is a sufficient margin so that the data can be captured
properly by the destination clock. This is shown by signal B2 in Figure
13. While the expected output would be B1, the actual waveform could
look like B2, but still there is no data loss in this case. However
there can be an issue of data incoherency as described in Section 2.3,
Figure 13. Clock edges come close together intermittently
a fast to slow crossing, data loss can occur, and in order to prevent
this, the source data should be held constant for a minimum of one
destination clock cycle. Again, this can be done by the use of a simple
This is the case when the phase
difference between the clocks can be very small at times and can remain
like that for several cycles. This is very similar to asynchronous
clocks except that the variable phase differences will be known and will
In Figure 14, clocks C1 and C2 have time
periods 10ns and 9ns respectively. It can be seen that the active clock
edges of both the clocks come very close together for 4 consecutive
cycles. In the first two cycles there is a possibility of a setup
violation (as the source clock is leading the destination clock) and in
the next two cycles there is a possibility of hold violation (as the
destination clock is leading the source clock).
Figure 14. Clock edges are close for consecutive cycles
In this case, there will be an issue of metastability and hence synchronization needs to be done.
from metastability there can be an issue of data loss also, even though
it is a slow to fast clock domain crossing. As can be seen from Figure
14, B1 is the expected output if there would have been no metastability.
However, the actual output can be B2. Here the data value ‘1’ is lost,
because in the first cycle the value ‘1’ is not captured due to setup
violation and in the second cycle the new value ‘0’ is incorrectly
captured due to hold violation.
In order to prevent data loss,
the data needs to be held constant for a minimum of two cycles of the
destination clock. This is applicable for both fast to slow as well as
slow to fast clock domain crossings. This can be done by controlling the
source data generation using a simple FSM. However, the data
incoherency issue can still be there.
In such cases, standard
techniques like handshake and FIFO are more useful to control data
transfer as they will also take care of the data incoherency issue.
Asynchronous Clock Domain Crossings
which do not have a known phase or frequency relationship between them
are known as asynchronous clocks. Whenever there is a clock crossing
between two asynchronous clocks, their active edges can arrive very
close together leading to metastability. Here the phase difference
between the clocks can be variable and unlike synchronous clocks it is
Proper synchronization needs to be done in the
destination domain to prevent metastability. Apart from that, there can
be problems of data loss and data incoherency (in both fast to slow as
well as slow to fast clock crossings). If the source and destination
clock frequencies are known, data loss can be prevented by holding the
source data constant for two cycles of the destination clock. However,
if the circuit is to be designed to be independent of clock frequencies,
handshake or FIFO techniques should be used to prevent metastability,
data loss and data incoherency.