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Removing pessimism and optimism in timing analysis
Naman Gupta - Freescale Semiconductor
10/1/2012 10:29 AM EDT
Pessimism an signal integrity
Pessimism in clock path during signal integrity (SI) analysis
The following figure shows how delay noise on a net (shown in red) can affect the slew of the adjacent nets and the way it can impact the setup and hold slack of the timing paths.
Fast switching on the aggressor net can improve the slew of the adjacent victim net and we might witness lesser delays. This would make it the path hold timing critical.
Similarly, slow switching rate or aggressor switching in the opposite direction can degrade the slew at the adjacent nets. This would make the path setup timing critical.
For all the cases that we have discussed so far: CPPR, CPR and different transition sense of launch and capture flops, timing engineers need to note the following:
Consider the following example:
Setup check is at least one cycle check, so there is a fair probability that the clock net might see different delay noise numbers (+Y on launch edge and –Y on capture edge) on launch and capture edges depending on the switching activity of the adjacent nets.
Hold is generally checked on the same clock edge, so the assumption of different delay noise numbers(+Y during launch and _-Y during capture) on clock edges for hold check is invalid and hence would add unnecessary pessimism in timing analysis. Therefore, one needs to remove this extra pessimism due to noise while doing hold timing analysis.
Conclusion
Accurate Timing Analysis is very important for success of any SoC. Any uncalled pessimism in timing analysis might require more time to fix the critical paths. On the other hand, any uncalled optimism might result in post silicon surprises. Timing derates are used to model OCV effects. Therefore, any pessimism or optimism in derate calculation, especially in clock path, can be detrimental. There exists both type of scenarios where applying derates on common clock path is justified and where it is not justified. In few cases design architecture and SoC use-case scenario must be understood properly to deduce whether derates need to be applied on common clock path or not.
About the author
Naman
Gupta is working as a Design Engineer with Freescale Semiconductor for
more than a year now. He is part of the Physical Design Team and
responsible for constraints development and timing closure. He has been
involved in both chip level and block level timing closure for various
SoCs at 55nm and 40nm. He can be reached via e-mail at
naman.gupta@freescale.com
If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you).
Pessimism in clock path during signal integrity (SI) analysis
The following figure shows how delay noise on a net (shown in red) can affect the slew of the adjacent nets and the way it can impact the setup and hold slack of the timing paths.
Figure 5: Noise on an adjacent net can impact setup and hold timing
Fast switching on the aggressor net can improve the slew of the adjacent victim net and we might witness lesser delays. This would make it the path hold timing critical.
Similarly, slow switching rate or aggressor switching in the opposite direction can degrade the slew at the adjacent nets. This would make the path setup timing critical.
For all the cases that we have discussed so far: CPPR, CPR and different transition sense of launch and capture flops, timing engineers need to note the following:
Consider the following example:
Figure 6: Effect of noise in setup and hold timing calculations
Setup check is at least one cycle check, so there is a fair probability that the clock net might see different delay noise numbers (+Y on launch edge and –Y on capture edge) on launch and capture edges depending on the switching activity of the adjacent nets.
Hold is generally checked on the same clock edge, so the assumption of different delay noise numbers(+Y during launch and _-Y during capture) on clock edges for hold check is invalid and hence would add unnecessary pessimism in timing analysis. Therefore, one needs to remove this extra pessimism due to noise while doing hold timing analysis.
Conclusion
Accurate Timing Analysis is very important for success of any SoC. Any uncalled pessimism in timing analysis might require more time to fix the critical paths. On the other hand, any uncalled optimism might result in post silicon surprises. Timing derates are used to model OCV effects. Therefore, any pessimism or optimism in derate calculation, especially in clock path, can be detrimental. There exists both type of scenarios where applying derates on common clock path is justified and where it is not justified. In few cases design architecture and SoC use-case scenario must be understood properly to deduce whether derates need to be applied on common clock path or not.
About the author
Naman
Gupta is working as a Design Engineer with Freescale Semiconductor for
more than a year now. He is part of the Physical Design Team and
responsible for constraints development and timing closure. He has been
involved in both chip level and block level timing closure for various
SoCs at 55nm and 40nm. He can be reached via e-mail at
naman.gupta@freescale.com
If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you).
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