Pessimism an signal integrity
Pessimism in clock path during signal integrity (SI) analysis
following figure shows how delay noise on a net (shown in red) can
affect the slew of the adjacent nets and the way it can impact the setup
and hold slack of the timing paths.
Figure 5: Noise on an adjacent net can impact setup and hold timing
switching on the aggressor net can improve the slew of the adjacent
victim net and we might witness lesser delays. This would make it the
path hold timing critical.
Similarly, slow switching rate or
aggressor switching in the opposite direction can degrade the slew at
the adjacent nets. This would make the path setup timing critical.
all the cases that we have discussed so far: CPPR, CPR and different
transition sense of launch and capture flops, timing engineers need to
note the following:
Consider the following example:
Figure 6: Effect of noise in setup and hold timing calculations
check is at least one cycle check, so there is a fair probability that
the clock net might see different delay noise numbers (+Y on launch edge
and –Y on capture edge) on launch and capture edges depending on the
switching activity of the adjacent nets.
Hold is generally
checked on the same clock edge, so the assumption of different delay
noise numbers(+Y during launch and _-Y during capture) on clock edges
for hold check is invalid and hence would add unnecessary pessimism in
timing analysis. Therefore, one needs to remove this extra pessimism due
to noise while doing hold timing analysis.
Timing Analysis is very important for success of any SoC. Any uncalled
pessimism in timing analysis might require more time to fix the critical
paths. On the other hand, any uncalled optimism might result in post
silicon surprises. Timing derates are used to model OCV effects.
Therefore, any pessimism or optimism in derate calculation, especially
in clock path, can be detrimental. There exists both type of scenarios
where applying derates on common clock path is justified and where it is
not justified. In few cases design architecture and SoC use-case
scenario must be understood properly to deduce whether derates need to
be applied on common clock path or not.
About the author
Gupta is working as a Design Engineer with Freescale Semiconductor for
more than a year now. He is part of the Physical Design Team and
responsible for constraints development and timing closure. He has been
involved in both chip level and block level timing closure for various
SoCs at 55nm and 40nm. He can be reached via e-mail at
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