FinFET structure design and variability analysis enabled by TCAD

The introduction by Intel of FinFET transistors at the 22nm mode culminates many years of research and development of a replacement transistor to the immensely successful planar MOSFET whose progressive miniaturization is largely responsible for the electronics revolution. The need for a successor to the planar MOSFET had long ago been identified. Starting with the 90nm process node, improved transistor performance was achieved with the introduction of stress into the transistor channel in a way that boosts the speed of the electrons and holes traveling within it. However, controlling the transistor leakage in the off-state became progressively more difficult. Keeping the electrons and holes under the electrostatic control of the gate electrode is key to controlling leakage current, but a number of so-called short channel effects undermine the gate control. The introduction of high-k dielectrics as the gate insulator at the 45nm process node effectively extended the life of the planar MOSFET for another two process nodes, but by the 22nm process node the planar MOSFET could hardly offer an attractive balance of performance and leakage.

Intel’s FinFETs thus mark the first fundamental change in transistor architecture since the time when the MOSFET replaced the bipolar transistor as the transistor of choice for logic applications. Its performance improvements over the preceding process node (see table) are a clear indication of the promise this technology holds. Although the manufacturing of FinFETs is more complex than manufacturing of its planar predecessor, Intel’s introduction is a testament to the inevitability of these devices.

While some 22nm processes will continue using planar MOSFETs, the introduction of FinFETs at 22nm has spurred the development of FinFET technology for the 14nm and smaller nodes at other leading integrated device manufacturers and foundries. With change afoot, the design community is rapidly familiarizing itself with these vertical devices and their novel characteristics, many of which revolve around the fin. From the perspective of a designer, the biggest change brought about by the introduction of FinFETs is the relinquishment of the transistor width as a continuous design variable, as the width now becomes quantized, proportional to the number of fins.

The circuit designers can benefit from the understanding of the technological considerations that go into defining the size, shape, doping and stress of the fin. Moreover, the dimensions of today’s and future FinFETs are so small that their electrical behavior is heavily susceptible to random process variations. In the remainder of this article we discuss these two points in more detail aided by the insight afforded by Technology CAD (TCAD) simulation, a simulation technology which is instrumental in optimizing the performance and manufacturability of FinFETs.