Geometric considerations in FinFETs
Geometric considerations in FinFETs
effectively surround the silicon channel with gates on three sides
(left, right and top of the fin). When the fin is thin enough, the
short-channel effects responsible for the leakage current become much
easier to mitigate under the tighter control of the three-sided gate.
practice, the design of a FinFET structure is a fairly complicated
process as it must contend with such diverse aspects as the integration
of high-k metal gates and stress engineering with the incorporation of
SiGe and Si:C source/drain regions for PMOS and NMOS, respectively. The
structural complexity of FinFETs is clearly seen in Figure 1. For the
remainder of this section we will focus on the aspects governing the
shape of the fin.
Figure 1. 3D representation of FinFET structure showing details of the epitaxially grown source/drain regions.
of the most interesting considerations in designing a FinFET is whether
to use sloped fin sidewalls. Stress simulations indicate that sloped
sidewalls are mechanically sturdier than vertical ones while impacting
electrical performance only minimally. Figure 2 shows a FinFET structure
stripped of its source and drain regions and gate electrode. Though the
FinFETs shown here are generic, their dimensions and design criteria
are representative of current technology. The shallow trench isolation
(STI) is filled with silicon dioxide up to a certain level that is below
the fin top by the fin height (that is, the geometric parameter H). The
high-k gate dielectric contains two monolayers of oxide interlayer
sandwiched between the high-k material (HfO2) and the fin.
2. Silicon fin shape options with vertical and sloped sidewalls. Corner
rounding radius is 2.5 nm. All three fin shapes have 15 nm wide fin
bottom, but different fin top widths. All fin shapes go through the same
process flow for a fair comparison.
The Synopsys TCAD simulators Sentaurus Process
and Sentaurus Device
are used to simulate the fabrication process and transistor electrical
performance. The fin channels have moderate doping, somewhat lower than
the planar MOSFET. The source and drain are doped with in situ
doping. The stress engineering, which includes the strained
source/drain and stress induced by the strained replacement metal gate,
is used to boost the on-state current. Here we contrast the performance
difference between rectangular and triangular fin cross sections.
3 depicts electron distributions across the fin of NMOS FinFET in the
off-state and on-state. In the off-state, the leakage happens in the
middle of the fin regardless of the fin shape. This is because the gate
controls the currents in the fin periphery that is close to the gate.
The middle of the fin is the most remote from the gate and the gate has
less leakage control over there. The leakage in the tapered fin is 17%
lower than in the rectangular fin with the same fin width at the fin
bottom due to the better gate control of the mid-fin.
3. Impact of fin cross section shape on NMOS FinFET performance. The
electron density maps are shown across the fin in the middle of the
The on-state current follows the fin
perimeter for all FinFET shapes. The 15 nm wide rectangular fin has 24%
higher on-current than for the tapered fin. This is due to the
combination of several factors, with 14% coming from the larger
perimeter length, and the remaining 10% due to no overlapping electron
distributions, and no thin-layer induced mobility degradation that
hamper the 5 nm wide fin top of the tapered FinFET.
gate control of the tapered fin improves the drain-induced barrier
lowering effect (DIBL) and reduces subthreshold slope (SS) from 85
mV/dec down to a respectable 77 mV/dec.
Similar analysis for the
PMOS is shown on Figure 4. What is different here is that the off-state
leakage happens mainly at the top of the fin rather than at mid-fin.
This is caused by the stress engineering being much stronger in the PMOS
FinFET than in the NMOS FinFET.
4. Impact of fin cross section shape on PMOS FinFET performance. The
hole density maps are shown across the fin in the middle of the channel
Specifically, the SiGe source/drain epitaxy with
over 50% Ge content introduces a huge stress in the PMOS fin,
illustrated by Figure 5. The SiGe-induced stress level is almost three
times higher than the NMOS fin stress. The goal of having such high
channel stress is to increase the hole mobility, which is achieved.
There’s also a side effect of stress-induced bandgap narrowing, with the
bandgap shrinking by about 200 mV at the fin top according to Figure 5.
Such severe bandgap narrowing at the fin top triggers increased hole
The main reason that stress distribution in the
fin is so non-uniform is the replacement metal gate (RMG) process. As
long as the dummy poly gate is in place, the fin stress is fairly
uniform. However, once the dummy poly is removed and its resistance to
the SiGe squeeze is gone, the PMOS fin gets the full force of the SiGe
source pushing from one side and the SiGe drain from the other. Stress
at the fin bottom barely changes, because it is still supported by the
adjacent STI, but stress at the fin top more than doubles because it is
narrow, exposed, and far away from the STI and the Si wafer below it.
Figure 5. PMOS FinFET stress map (left) and stress-induced bandgap narrowing (right).
back to Figure 4, the off-state current of the tapered PMOS FinFET is
9% lower than for the rectangular one. The difference is so small
because the RMG stress-induced bandgap narrowing and the subsequent
leakage are stronger in the tapered fin with narrow, more vulnerable fin
The on-state current of the tapered PMOS FinFET is only 5%
lower than for the rectangular one, with the respective subthreshold
slopes of 66 mV/dec and 73 mV/dec. The difference in subthreshold slopes
mainly indicates the DIBL control, and it is interesting to observe
that the DIBL and the SS numbers are better for the PMOS compared to the
NMOS. The reason is the smaller quantum separation of the holes
relative to the electrons.
The holes on the on-state current
patterns on Figures 3 and 4 hug the fin perimeter closer to the fin
surface than the electrons and therefore experience tighter capacitance
effective thickness (CET) and better gate control.