TSMC says it's ready for 20-nm designs

LONDON – Foundry Taiwan Semiconductor Manufacuturing Co. said this week its has prepared reference design flows in support of 20-nm planar CMOS and chip-on-wafer-on-substrate (CoWoS) assembly within its Open Innovation Platform (OIP). Both technologies are open for design starts.

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The 20-nm reference flow culminates in double-patterning-aware place and route to allow manufacturing using deep ultraviolet immersion lithography. Leading EDA vendors' tools have been qualified to work with the 20-nm process on timing, physical verification and design-for-manufacturing. In addition, TSMC and its ecosystem partners are developing 20-nm IP for double-patterning compliance to accelerate 20-nm adoption.

TSMC did not list specific vendors' 20-nm compatible tools, but the reference design flow provides a direct link with simulators for voltage-dependent design rules. An RF reference design kit provides high-frequency design guidelines, including 60-GHz RF model support, electromagnetic characterization and integrated passive device support.

The 20-nm high-k metal gate CMOS planar process is expected to begin volume production in 2013.

The CoWoS reference design flow enables multiple die to be integrated on an interposer. It is a heterogeneous approach in the sense that the interposer, or substrate, usually made of silicon, is unlikely to be in a leading-edge process. Similarly, multiple die on the interposer can be made using different processes.

The flow has now been validated with silicon runs and could be adopted to support high-bandwidth and lower power connections between chips, TSMC said. It includes: management of placement and routing of bumps, pads, interconnections and C4 bumps; an innovative combo-bump structure; accurate extraction and signal integrity analysis of high-speed interconnects between dies; thermal analysis from chip to package to system; and an integrated testing methodology for die-level and stacking-level tests.


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