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Memory solution addressing power and security problems in embedded designs
10/22/2012 12:29 AM EDT
Challenging design requirements
Challenging design requirements
An embedded design today might contain the elements shown in Fig. 1—an MCU with SRAM and an external EEPROM/Flash for firmware and data storage, creating significant power limitations in the design. The most obvious is the on-board SRAM, which continuously draws power to maintain stored data. At smaller process geometries, 65nm and below, for example, the SRAM drain is aggravated by the leaky nature of the processes themselves.
Placing the SRAM in non-retentive standby mode has measurable power and performance implications. Power loss from communicating with external devices is caused by the higher voltage and capacitance of the external interconnect (P=CV2F, where power P is equal to CV2F where C is capacitance, V is voltage and F is frequency). Restoring program code from external EEPROM or serial Flash every sleep exit takes too much time, eliminating the instant-on capability.
NVM technology that uses other storage elements—eFuse and ROM—addresses the power problem but has its own limitations. The eFuse has limited storage capacity due to its low density. ROM offers great cost, performance, and power capability, but is limited by its design, validation, and manufacturing cycle. Data is stored in the silicon of the ROM array using via or diffusion. ROM contents must be included in the GDSII of the SoC prior to mask making. Once the SoC is fabricated, changing its ROM contents requires a new mask set and full manufacturing cycle, both costly in time and money. Using many ROM versions of the same base design is costly and presents operations challenges (e.g. supply forecasting and inventory management; not having the right product mix at the right time is opportunity lost).
Challenging design requirements
An embedded design today might contain the elements shown in Fig. 1—an MCU with SRAM and an external EEPROM/Flash for firmware and data storage, creating significant power limitations in the design. The most obvious is the on-board SRAM, which continuously draws power to maintain stored data. At smaller process geometries, 65nm and below, for example, the SRAM drain is aggravated by the leaky nature of the processes themselves.
Fig. 1: A typical wireless SoC design
Placing the SRAM in non-retentive standby mode has measurable power and performance implications. Power loss from communicating with external devices is caused by the higher voltage and capacitance of the external interconnect (P=CV2F, where power P is equal to CV2F where C is capacitance, V is voltage and F is frequency). Restoring program code from external EEPROM or serial Flash every sleep exit takes too much time, eliminating the instant-on capability.
NVM technology that uses other storage elements—eFuse and ROM—addresses the power problem but has its own limitations. The eFuse has limited storage capacity due to its low density. ROM offers great cost, performance, and power capability, but is limited by its design, validation, and manufacturing cycle. Data is stored in the silicon of the ROM array using via or diffusion. ROM contents must be included in the GDSII of the SoC prior to mask making. Once the SoC is fabricated, changing its ROM contents requires a new mask set and full manufacturing cycle, both costly in time and money. Using many ROM versions of the same base design is costly and presents operations challenges (e.g. supply forecasting and inventory management; not having the right product mix at the right time is opportunity lost).
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