Electrically-aware design improves analog/mixed-signal productivity

Electromigration and its causes
Electromigration and its causes

Electromigration (EM) effects can seriously damage interconnect wires and vias, having an adverse impact on IC reliability. Electrically-aware design provides new in-design methodology opportunities for EM verification, and the same general methodology could be applied to a range of in-design electrical checking and simulation solutions.

EM is the transport of material in a solid conductor that results from collisions between the flow of electrons and metal atoms in the interconnect. Proportional to the current per unit area, the continual movement of metal atoms from their lattice position can lead to a degradation in performance as the resistance of the interconnect increases. At some point the wire eventually fails, creating an electrical open (void) or short connection (hillock) downstream.

The dominant factor in determining mean time to failure (MTTF) is the current density. Since current density depends on the wire geometry, it cannot be determined until the routed net is generated. Given that the width of the wire or via is a variable, designers need to know whether the current flowing through that particular area has exceeded the maximum allowed current. The maximum current limit for a given geometry is expressed as rules that every wire segment or via must adhere to for a specified operating or maximum temperature. This set of rules is contained in a technology file that is computed and distributed according to each process technology specification.

With the aggressive scaling of interconnect geometries at advanced technology nodes, the EM effects are dependent not only on the local current density of a geometric wire segment or via, but also on the homogeneity of the current flow through a region. As such, current density limits or rules vary based on not just each geometric dimension of the wire segments and vias, but on the geometries of the connecting wires and vias as well.

There are additional complications. There is a minimum length below which the net won't fail due to EM, commonly referred to as Blech length. This adds another dimension to the problem of sizing a wire for EM. The EM rules for a metal layer are specified in buckets for different limits based on the width and length of shapes on the layer. Without assistance from an EDA tool, it would be cumbersome for a layout engineer to route nets on various layers and account for the ever-increasing number of EM rules associated with these buckets.

The EM rules become even more complicated when vias and contacts are considered. Traditionally, single via or contact cuts had a current density number associated with them, while clusters of vias would have more relaxed rules. At advanced technology nodes, a single via or contact will have different current density limits based on different shapes (e.g. square or rectangular). This issue is compounded when additional conductors are connected to the via(s) and the current density limits can change based on the width and length of the connecting conductors.

This behavior is illustrated in Figure1 with three interconnect examples that are based on different widths and lengths of connecting wires. All three have different current density (EM) limits. Each has an upper and lower interconnect wire connected through the same via shape, but each example forms a different geometric profile where the length or width dimensions of the interconnect differ.

The leftmost connection in the figure has the shortest lengths in the dimension of the upper and lower interconnect wires, with the result that the connecting via cut has the highest current density limit and thus can carry the most current without violating the limit. The middle connection has the same interconnect wire width as the left one, but the wire lengths of the upper and lower interconnect are much longer. The impact is that the current density limit for the via cut is lower than the left example. As such, the middle connection can carry less current and remain within the EM-related reliability limits.

In the rightmost connection in Figure 1, the upper and lower interconnect lengths are the same but the width of the wires coming into the via are reduced. The result is that the current density limit for the via cut is significantly reduced from the middle and leftmost examples. Note that in all three examples the via geometry is the same and, if examined without any context of the surrounding wire geometry, it is impossible to know which current density limits to apply.



In addition to the geometric properties of the interconnect, the underlying topology of the routing can also significantly change the distribution of current flow and, subsequently, current densities. Thus the same geometric description (such as a specific width and length of a wire) may or may not meet pre-specified current density limits, depending on the topology of the surrounding interconnect.

Figures 2 and 3 highlight a case where the incoming current to the MOS device may be connected to the strap in two different locations. In Figure 2, the current is sourced into one side of the M2 strap, which results in a large amount of current flowing through the strap to reach the M1 vertical finger connections on the other end. Color coding is used to indicate the proximity of that wire location to the specified current density limit. In this case, the green coding indicates that the current is far from reaching the limit; red coding represents that the current is over the limit for that particular wire segment.


In Figure 3, the incoming current is connected to the middle of the M2 strap and, as such, the current is distributed more evenly throughout the source vertical connections (fingers). As the color coding indicates, the current limit is not exceeded, even though the geometric properties of the fingers, strap, and incoming wire are very similar—the primary distinction being where the connection has been made. This example also illustrates why it is difficult to specify current-correct routing decisions a priori without knowledge of the underlying topology. This rather simple case was chosen to illustrate the problem, but there are many such cases where the correction to the routing topology is not straightforward, often resulting in a cycle of layout modification, extraction, and analysis.


The prior examples illustrate just some of the complexities of designing at advanced nodes. As the rules become more geometry-dependent, it will become increasingly difficult to know which wire segments or vias to fix and how to do so without creating another violation. The following paragraphs propose an electrically-aware design methodology for in-design EM checking that improves productivity while reducing the risk and uncertainty of moving to advanced nodes.