Electrically-aware design improves analog/mixed-signal productivity

Electrically-aware, “in design” verification
Electrically-aware, “in design” verification

As shown in Figure 4, the in-design flow begins with creation of a schematic that is simulated and modified to meet the designer’s specifications. After the ideal, pre-layout simulation is completed, the currents at each terminal are saved. A testbench setup is configured to generate the average, RMS, and peak currents necessary for EM checking.


After device creation and placement, routing is initiated. For a given interconnect geometry to be routed, the EM limits should verify that it is below the maximum current or current density allowed for each segment of the net. To solve the current flow, parasitics need to be extracted as the net is routed and sized. The extracted parasitics are then used to solve current distribution throughout the wires and vias that constitute a net, with extraction and current solving occurring as the net is created.

Foundries create and maintain EM-related current density limits to ensure reliability of the manufactured device over years of operation at nominal and elevated temperatures. These limits are provided in a technology file and, as discussed above, are growing increasingly complex with geometric dependencies. During layout creation, the limits from the techfile are loaded and made available for in-design verification. The current limits and the solved currents for each geometric shape or set of net shapes are checked as layout edits are made.

Use models for electrically-aware, in-design verification and optimization fall into three basic categories: manual, assisted, and automatic. It is likely that a manual use mode will be adopted by users first until they are confident that in-design solutions provide accurate problem detection and correction. The results can be displayed in real time as color-coded overlays on the layout (Figures 2 and 3), or a threshold may be set where only violations are shown.

When violations are identified in the GUI, the user can simply click on the net and resize the wire. Incremental electrical analysis immediately checks the edit, and when the wire is sufficiently wide, the display is updated accordingly (as indicated with the green overlay). Sometimes resizing may not be sufficient or desirable. In those cases, movement of the route location may be necessary, as shown in Figure 3. Once the net passes verification, the user can move to the next net to be routed.

In the assisted use mode, once a current density limit violation is identified, the tool will compute and display a suggested fix such as “increase wire width by 100%.” The user would have the option to review and approve fixes individually or simply approve all. As the user becomes more comfortable with the suggested modifications from the tools, in-design solutions can drive more automatic wire sizing and routing changes during the routing process. This approach is often referred to as current-driven routing, which may take the form of a feed-forward approach (a topology editor and wire size selection are used to select net properties prior to physical routing), or a feedback approach (an optimization loop and cost function are used to iterate after the net is routed until the acceptance criteria are met).