analog/mixed-signal chips, the reduction of uncertainty during physical
design will similarly reduce overly conservative design practices and
improve return on investment in terms of in-silicon performance and
profitability. Electrically-aware, in-design verification methodologies
will reduce uncertainty through electrical assessment, verification, and
optimization of each incremental physical design decision. One of the
largest contributors to electrical uncertainty is the current density
limits imposed by electromigration, and most believe these limits will
become even more complex at 20nm and beyond.
In this article,
new methodologies have been proposed to incrementally extract parasitic
and check current-related limits as each net is routed. Initial
solutions will likely identify solutions and provide users with
assistance in resolving any problems. As users become more confident in
the ability of in-design solutions to automatically correct such issues,
the introduction of current-driven routing methodologies and solutions
will be addressed. These solutions will evolve toward the ultimate goal,
which is an EDA solution that generates layout that is electrically
correct by construction and minimizes turnaround time for
Electrically-aware design is discussed in more detail in the recently published Cadence® Mixed-Signal Methodology Guide .
Mixed-Signal Methodology Guide: Advanced Methodology for AMS IP and SoC
Design, Verification, and Implementation, J. Chen, et. al, eds.,
Cadence Design Systems, 2012.
About the authors
White received a Doctor of Science Degree in Electrical Engineering and
Computer Science from the Massachusetts Institute of Technology in
2001. He currently directs R&D for Virtuoso Electrically Aware
Design products at Cadence Design Systems in San Jose, California. He
joined Cadence in 2006 through the acquisition of Praesagus, a software
company he co-founded in 2001 and where he served as Chief Technology
Officer until the merger. Dr. White has served as a member of the
Advisory Board for the National Science Foundation (NSF) in Washington
D.C. as well as advisory boards at MIT and early stage companies.
Akshat Shah received his Bachelors of Science Degree in Electrical and Computer Engineering from Carnegie Mellon University and his Masters in Business Administration from the University of Pittsburgh. Akshat is currently the Product Engineering Director for Virtuoso platform. His team is responsible for the Virtuoso Front-End, the Electrically Aware Design flow and the 20nm Advanced Nodes Flow. He joined Cadence thru the Neolinear acquisition in 2006 where he was a Product Engineer and drove the NeoCircuit and NeoCell products which are now part of the Virtuoso platform.
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