Design Article
Comment
LJohnso58
While this article is focused on the chip creation process, it is equally ...
Guru of Grounding
Although this piece is so full of "marketspeak" that I needed to translate every ...
Electrically-aware design improves analog/mixed-signal productivity
David White and Akshat Shah - Cadence Design Systems
10/29/2012 9:01 AM EDT
Conclusion
Conclusion
For analog/mixed-signal chips, the reduction of uncertainty during physical design will similarly reduce overly conservative design practices and improve return on investment in terms of in-silicon performance and profitability. Electrically-aware, in-design verification methodologies will reduce uncertainty through electrical assessment, verification, and optimization of each incremental physical design decision. One of the largest contributors to electrical uncertainty is the current density limits imposed by electromigration, and most believe these limits will become even more complex at 20nm and beyond.
In this article, new methodologies have been proposed to incrementally extract parasitic and check current-related limits as each net is routed. Initial solutions will likely identify solutions and provide users with assistance in resolving any problems. As users become more confident in the ability of in-design solutions to automatically correct such issues, the introduction of current-driven routing methodologies and solutions will be addressed. These solutions will evolve toward the ultimate goal, which is an EDA solution that generates layout that is electrically correct by construction and minimizes turnaround time for analog/mixed-signal designs.
Electrically-aware design is discussed in more detail in the recently published Cadence® Mixed-Signal Methodology Guide [1].
References
[1] Mixed-Signal Methodology Guide: Advanced Methodology for AMS IP and SoC Design, Verification, and Implementation, J. Chen, et. al, eds., Cadence Design Systems, 2012.
About the authors
David
White received a Doctor of Science Degree in Electrical Engineering and
Computer Science from the Massachusetts Institute of Technology in
2001. He currently directs R&D for Virtuoso Electrically Aware
Design products at Cadence Design Systems in San Jose, California. He
joined Cadence in 2006 through the acquisition of Praesagus, a software
company he co-founded in 2001 and where he served as Chief Technology
Officer until the merger. Dr. White has served as a member of the
Advisory Board for the National Science Foundation (NSF) in Washington
D.C. as well as advisory boards at MIT and early stage companies.
Akshat Shah received his Bachelors of Science Degree in Electrical and Computer Engineering from Carnegie Mellon University and his Masters in Business Administration from the University of Pittsburgh. Akshat is currently the Product Engineering Director for Virtuoso platform. His team is responsible for the Virtuoso Front-End, the Electrically Aware Design flow and the 20nm Advanced Nodes Flow. He joined Cadence thru the Neolinear acquisition in 2006 where he was a Product Engineer and drove the NeoCircuit and NeoCell products which are now part of the Virtuoso platform.
If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you).
Conclusion
For analog/mixed-signal chips, the reduction of uncertainty during physical design will similarly reduce overly conservative design practices and improve return on investment in terms of in-silicon performance and profitability. Electrically-aware, in-design verification methodologies will reduce uncertainty through electrical assessment, verification, and optimization of each incremental physical design decision. One of the largest contributors to electrical uncertainty is the current density limits imposed by electromigration, and most believe these limits will become even more complex at 20nm and beyond.
In this article, new methodologies have been proposed to incrementally extract parasitic and check current-related limits as each net is routed. Initial solutions will likely identify solutions and provide users with assistance in resolving any problems. As users become more confident in the ability of in-design solutions to automatically correct such issues, the introduction of current-driven routing methodologies and solutions will be addressed. These solutions will evolve toward the ultimate goal, which is an EDA solution that generates layout that is electrically correct by construction and minimizes turnaround time for analog/mixed-signal designs.
Electrically-aware design is discussed in more detail in the recently published Cadence® Mixed-Signal Methodology Guide [1].
References
[1] Mixed-Signal Methodology Guide: Advanced Methodology for AMS IP and SoC Design, Verification, and Implementation, J. Chen, et. al, eds., Cadence Design Systems, 2012.
About the authors
David
White received a Doctor of Science Degree in Electrical Engineering and
Computer Science from the Massachusetts Institute of Technology in
2001. He currently directs R&D for Virtuoso Electrically Aware
Design products at Cadence Design Systems in San Jose, California. He
joined Cadence in 2006 through the acquisition of Praesagus, a software
company he co-founded in 2001 and where he served as Chief Technology
Officer until the merger. Dr. White has served as a member of the
Advisory Board for the National Science Foundation (NSF) in Washington
D.C. as well as advisory boards at MIT and early stage companies. Akshat Shah received his Bachelors of Science Degree in Electrical and Computer Engineering from Carnegie Mellon University and his Masters in Business Administration from the University of Pittsburgh. Akshat is currently the Product Engineering Director for Virtuoso platform. His team is responsible for the Virtuoso Front-End, the Electrically Aware Design flow and the 20nm Advanced Nodes Flow. He joined Cadence thru the Neolinear acquisition in 2006 where he was a Product Engineer and drove the NeoCircuit and NeoCell products which are now part of the Virtuoso platform.If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you).
|
|
|
|
|
Navigate to related information
Ron.Koths
11/1/2012 11:37 AM EDT
I couldn't agree more, why can't my layout software show me a 3D projection with lines of force or a colored cloud representing the magnetic field of the trace I'm laying down, as I route it.
Sign in to Reply
Guru of Grounding
11/1/2012 2:45 PM EDT
Although this piece is so full of "marketspeak" that I needed to translate every sentence to get the drift, the point is an excellent one. Those of us who work in the low-level, wide dynamic-range analog world called "audio" learned long ago that "auto-routing" circuit boards leads most often to disaster. Given the generally poor state of analog skill, an auto-router that embraced common-impedance coupling, magnetic loop areas, and electric field coupling could eliminate thousands of badly-designed products. In audio, most of these bad designs pass bench tests but have horrible problems when connected into real-world systems where power-line noise and significant shield currents exist. I dub many of these "sensitive" designs as "power-line primadonnas".
Sign in to Reply
LJohnso58
11/1/2012 2:47 PM EDT
While this article is focused on the chip creation process, it is equally applicable to the board level creation process, also at the advanced nodes. High density designs in this arena also need electrical awareness from top to bottom. EDA vendors are starting to address this with integrated tool suites incorporating schematic, simulation, PCB and documenation all rolled into one. These tools don't go far enough yet. We routinely work at geometries on the PCB that once were reserved for silicon. We have mixed signal and have to do current density analysis as well as thermal flow analysis. SI analysis is also an integral part of PCB layout and unfortunately, very few DRC tools understand how to check for unbroken return paths, proper termination placement and unexpected radiation. Parasitics from the layout need to be extracted and moved back to the simulation environment to tighten the design so it can be adjusted prior to finalization. Gone are the days when we can just throw a design over the wall to the next step in the process. More and more, the entire vertical process belongs in the hands of a single engineer, and the tools need to support that approach. As no engineer can be expected to know and comprehend all the technologies that may appear on a board,a team is now divided horizontally, so the tools need to permit collaborative efforts. Such tools are just starting to emerge, but not all are on the band wagon. At this time, only a small percentage of project absolutely fall into this category, but as time moves on, these sorts of things will become the norm. Just think of the many tools we have for board and system design that used to be the province of silicon designers. Perhaps its time for that lag to disappear.
Sign in to Reply