Two solido and TSMC case studies
Two solido and TSMC case studies
we describe two memory circuit examples, which illustrate the benefits
of combining TSMC’s statistical device models with the Solido HSMC tool.
The first example is on a 6 transistor bitcell, using
statistical device models from the TSMC 28nm PDK. With 6 devices, it has
60 local process variables. As a reference, we generated 1M Monte Carlo
samples, then simulated them and measured read current (cell_i). We
plotted those in a normal quantile (NQ) plot, shown below. Each dot is a
Monte Carlo sample point.
NQ plots make it easier to see the
tails of a distribution. In a NQ plot, the x-axis is the circuit output
and the y-axis is the cumulative distribution function (CDF) scaled
exponentially. In a circuit with linear response of output to process
variables, the NQ curve will be linear – a straight line of dots from
the bottom left to the top right. Nonlinear responses give rise to
nonlinear NQ curves. In the bitcell NQ plot, the bend in the middle of
the curve indicates a quadratic response in that region. The sharp
dropoff in the bottom left shows that for process points in a certain
region, the whole circuit shuts off, for a current of 0. The curve’s
shape clearly indicates that any method assuming a linear response will
be extremely inaccurate, and even a quadratic response will suffer.
the same bitcell read current problem, we then ran Solido HSMC, using
100M generated Monte Carlo samples. In 5500 simulations, it accurately
found the tail of the read current distribution, shown as the red dots
in the upper right corner of the NQ plot. With this tail, the designer
can estimate yield (given a target spec), or a spec (given a target
yield). Traditional Monte Carlo sampling would have needed 100M
simulations to get the same tail information that HSMC got in 5500
simulations. Furthermore, each of the red dots is an actual point in
process variable space, which can be used as a corner to design against.
This makes it easy to do rapid design iterations: the designer can test
a design point by doing just one simulation on the statistical corner
to measure read current; while implicitly designing against the target
second case is a sense amp delay, having 15 devices and 150 process
variables, also using statistical device models from the TSMC 28nm PDK.
Once again, we generated and simulated 1M Monte Carlo samples for
reference. The NQ plot is shown below. The three vertical “stripes” of
points indicate three distinct sets of values for delay -- a trimodal
distribution. The jumps between the strips indicate discontinuities: a
small step in process variable space sometimes leads to a giant shift in
Such strong nonlinearities will make linear and
quadratic models fail completely; in this case they would completely
miss the mode at the far right at delay of about 1.6 ns. The NQ plot
below also illustrates Solido HSMC results (in red) on 150-variable
sense amp, where Solido HSMC used 100M generated Monte Carlo samples. In
<10K simulations, Solido HSMC effectively found the tails of each
article reviewed the performance and yield challenges that memory
designers face at 28nm, and the market pressures driving those
challenges. It then describes how Solido assisted to provide a path for
memory designers to rapidly and accurately estimate the yields of their
memory designs, using TSMC statistical models and PDKs combined with
Solido’s High-Sigma Monte Carlo (HSMC) tool.
I wish to thank Bob
Mullen, Technical Manager at TSMC for helping organize this article and
apply some of the Solido solutions to TSMC.