Design Article
Tell us What You Think
We want to know what you thought about this Design. Let us know by adding a comment.
Synopsys, TSMC enable litho compliance checking for 20 nm
11/14/2012 1:32 PM EST
SAN FRANCISCO—EDA and IP vendor Synopsys Inc. announced Wednesday (Nov. 14) the delivery of lithography compliance checking technology for Taiwan Semiconductor Manufacturing Co. (TSMC)'s 20-nanometer DFM data kit (DDK) encapsulated with Synopsys Proteus mask synthesis technologies.
As a result of the design-for-manufacturing collaboration between TSMC and Synopsys, the compliance checking engine in the DDK helps designers identify lithography-related problems early in the design development phase, avoid litho-related manufacturing issues and late-stage schedule slips resulting from re-design, Synopsys (Mountain View, Calif.) said.
The TSMC 20-nm DDK complements traditional physical verification rules with a highly accurate simulation-based solution to identify design non-compliance using a direct simulation of the manufacturing process, Synopsys said. Lithography correction and verification tools used in the manufacturing mask synthesis flow are embedded in the DDK, resulting in accurate hotspot detection to avoid litho-related manufacturing issues, according to the firm.
"Our close collaboration with TSMC to develop the 20-nanometer DDK helps bridge the gap between design and manufacturing, enabling TSMC to work efficiently with their customers to achieve faster volume ramps and more predictable product release cycles," said Tom Ferry, senior marketing director of the Silicon Engineering Group at Synopsys, in a statement.
Related stories:
As a result of the design-for-manufacturing collaboration between TSMC and Synopsys, the compliance checking engine in the DDK helps designers identify lithography-related problems early in the design development phase, avoid litho-related manufacturing issues and late-stage schedule slips resulting from re-design, Synopsys (Mountain View, Calif.) said.
The TSMC 20-nm DDK complements traditional physical verification rules with a highly accurate simulation-based solution to identify design non-compliance using a direct simulation of the manufacturing process, Synopsys said. Lithography correction and verification tools used in the manufacturing mask synthesis flow are embedded in the DDK, resulting in accurate hotspot detection to avoid litho-related manufacturing issues, according to the firm.
"Our close collaboration with TSMC to develop the 20-nanometer DDK helps bridge the gap between design and manufacturing, enabling TSMC to work efficiently with their customers to achieve faster volume ramps and more predictable product release cycles," said Tom Ferry, senior marketing director of the Silicon Engineering Group at Synopsys, in a statement.
Related stories:
- Demystifying DDR4 SDRAM for Embedded Applications
- EDA/IP weekly roundup – November 14th
- Synopsys announces new generation of STAR Memory System
- Synopsys unveils memory test and repair tool
- Myths, hype and the building blocks of SoCs
|
|
|
|
|
Navigate to related information