new waveform generation results were compared to the gate-level
waveform produced by traditional, simulation-based generation. The new
flow produced a gate-level waveform identical or almost identical to the
traditional approach. Analyses and comparisons were performed on five
use cases with the following results:
- Using the new flow
from time zero on a design, excluding its memories, resulted in exactly
the same waveform as that of the traditional gate-level flow with zero
- Repeating the previous comparison on the design, including its memories, yielded the same result.
the new flow to generate a waveform from a specific time-point (not
zero) for the design, excluding its memories, produced the same waveform
as gate-level simulation, with the simulation waveform dumped from that
- Repeating the previous comparison on the
design, with memories, the new flow achieved almost 100% accuracy with
respect to gate-level simulation. The only difference was in the path
from the memory outputs until the first sample. This small discrepancy
had no effect on the power analysis result. After adding hard macro
outputs, such as memory data out pins, to the mapping file, the
methodology again achieved 100%.
- Using the new flow on a
design, driving only essential inputs such as clocks, test mode pins
and special controls, produced the same waveform as gate-level
simulation for all “flip-flop to flip-flop” paths. Only the path from
input to the first sample was not correlated. On a large design
containing many such paths, the correlation was better than 99%. This
case is typical for waveform generation using the post-place and route
netlist, which is the generation method of choice for power estimation.
Examples of the resulting gate-level waveform generation and power estimation performance include:
generation for the gate-level environment (pre-place and route) of a
block with approximately 1.4 million placement elements, about 1,000
input ports: 100μs (about 40K cycles) took about 60 minutes. The total
time for power estimation was two hours, including loading the database
into PrimeTime PX, generating the mapping file, running the tool,
generating the SAIF file from the gate-level waveform, and calculating
power consumption with PrimeTime.
- Waveform generation for a
block of approximately 1.6 million placement elements: 400μs (about 150K
cycles) completed in 90 minutes. The entire power estimation flow
executed in about 2.5 hours.
- Waveform generation of a block of
approximately 1.4 million placement elements took about an hour, using
the post place-and-route netlist together with an RTL FSDB generated in
an RTL environment that used a Specman stub to replace several CPUs. In a
previous generation of this block, power estimation on the post
place-and-route netlist was abandoned after three engineer-weeks of work
because the effort required to match the stub interface to the post
place-and-route interface was excessive.
teams can further automate and extend the analysis capabilities of this
new gate-level waveform generation methodology by integrating
Automated Debug System into the flow, using the Verdi Interoperability
Apps (VIA) platform. The entire foregoing flow can be integrated with
Verdi’s GUI and database infrastructure in order to incorporate the
results from downstream power estimation tools. This enables design
teams to correlate power characteristics with the relevant design
instances, thus greatly increasing visibility and the accuracy of
gate-level waveform is critical to the task of obtaining accurate power
estimation. Historically, though, generating this waveform has required
a great deal of time and effort — and design teams often run out of
time. The new methodology described here automates the waveform
generation task, producing a waveform identical to that derived from
gate-level simulation, and reducing the time required to complete power
estimation from weeks to hours. The automated flow enables design teams
to perform power estimation after each synthesis and after each place
and route. They no longer have to wait until the end of the project to
accurately estimate power. Instead, they can now estimate power
accurately early in the design process, where it is much easier to make
The authors would like to thank the following for their contribution to the success of the project:
Oren Unger, senior CAD manager at CSR, who wrote the scripts for the mapping file.
Arnold Sher, applications consultant at SpringSoft, who guided CSR in the adoption of the solution.
About the Authors
Turbovich is SOC VLSI Infrastructure Manager at Cambridge Silicon
Radio. He is responsible for the development of working environment
methodologies that improve design teams’ efficiency, quality and
productivity. He has over 13 years of VLSI verification and design
experience. Before joining CSR, Ophir worked at Mellanox Technologies.
He has a B.Sc. in computer engineering from the Technion, Israel
Institute of Technology.
Thomas Li is Product Marketing Director
at SpringSoft, responsible for the company’s debug automation products.
He has over 15 years of EDA industry experience, having held technical
positions in product marketing, applications engineering and design
services consulting. Before joining SpringSoft, Thomas worked at
Synopsys and Mentor Graphics. He has a M.S.
degree in Computer Science & Information Engineering from National
Chung-Cheng University, Taiwan, and an MBA from Saint Mary’s College, California.
and Siloti are trademarks of SpringSoft, Inc. All other trademarks and
registered trademarks are the property of their respective owners.
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