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High-performance hardware models for system simulation
Chris Eddington - Synopsys
12/11/2012 11:37 AM EST
Design Example
Digital radio design example (DDC block)
The benefits of automatic C-model generation are illustrated using a Digital Down Converter (DDC) example. The DDC requirements include a frequency synthesizer, I/Q mixer, followed by a 5-stage CIC decimation filter, a 20th order low-pass compensation filter, and a 39th order matched filter to attenuate the out-of-band signals. A CPU interface (AMBA AXI3) is provided as an RTL block and provides the coefficients for the matched filter, the carrier frequency, and the initial carrier phase for QAM demodulation. The block diagram of the DDC is shown below:
High-level design and verification
The DDC is designed in Simulink using Synphony Model Compiler as shown below. The datapath is built with high-level blocks from the Synphony Model Compiler library, while the AMBA AXI3 CPU interface is written in Verilog RTL using the Synphony RTL Encapsulation block to instantiate it into the Simulink model.
Creating and running C models of the DDC
Synphony Model Compiler creates a C-model as part of the high-level synthesis process, as shown in the figure below. Makefile options and simulation wrappers are also generated so the model can be compiled for various simulation environments:
The design is simulated for one million input samples in the associated testbench. The simulation times are shown in the following table. Significant performance improvements over Simulink and RTL simulation are realized using the C model even though cycle accuracy is maintained.
Summary
Hardware models with the right combination of accuracy and simulation performance can accelerate integration and system verification tasks -- if they are available early enough in the design flow. With the right balance of performance, accuracy, and flexibility, automatic C-model generation tools such as Synphony Model Compiler can achieve significant simulation speedup and eliminate the hardware model availability problem. Furthermore, the availability of these models can shorten integrated verification and system validation cycle by weeks or months compared to traditional methods.
For more information about Synopsys’ Synphony Model Compiler, please click here.
About the author
Chris Eddington is Sr. Technical Marketing Manager for High-Level Synthesis at Synopsys and has over 20 years of experience in ASIC and FPGA design. He has held various roles in technical marketing, algorithm development and IC design at semiconductor companies doing video and audio conferencing ICs and wireless communications systems. He holds an MS engineering degree from the University of Southern California and an undergraduate degree in Physics and Math from Principia College.
If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
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Digital radio design example (DDC block)
The benefits of automatic C-model generation are illustrated using a Digital Down Converter (DDC) example. The DDC requirements include a frequency synthesizer, I/Q mixer, followed by a 5-stage CIC decimation filter, a 20th order low-pass compensation filter, and a 39th order matched filter to attenuate the out-of-band signals. A CPU interface (AMBA AXI3) is provided as an RTL block and provides the coefficients for the matched filter, the carrier frequency, and the initial carrier phase for QAM demodulation. The block diagram of the DDC is shown below:
High-level design and verification
The DDC is designed in Simulink using Synphony Model Compiler as shown below. The datapath is built with high-level blocks from the Synphony Model Compiler library, while the AMBA AXI3 CPU interface is written in Verilog RTL using the Synphony RTL Encapsulation block to instantiate it into the Simulink model.
Figure 1: Block diagram of a digital downconverter design example
Figure 2: Mixed high-level datapath and RTL design with multiple sample rates
The
DDC verification is done at a high level using MATLAB scripts to create
stimulus and compare the output performance to some verification
criteria such as SNR, SFDR, mask rejection, adjacent channel rejection,
and other domain-specific parameters. For illustration, we use a
simplified example of approximately 4000 output samples, enough to
analyze the spectrum with a 4K Fast Fourier Transform (FFT). Since the
decimation factor for the entire filter chain is 256, the model must be
simulated for at least 256*4000 = 1M input samples for this case. In a
real verification scenario the simulations would require many more
samples and there would be many simulations to cover multiple criteria
in the specification.Creating and running C models of the DDC
Synphony Model Compiler creates a C-model as part of the high-level synthesis process, as shown in the figure below. Makefile options and simulation wrappers are also generated so the model can be compiled for various simulation environments:
- Direct Execution (run the testbench at the OS command line)
- Simulink
- DPI (or PLI) for RTL simulators
- SystemC
- Custom simulation environments
Figure 3: Automatic C-model generation from RTL and/or Simulink blocks
One
particular challenge is managing multiple sample rates and clock
domains. The ability to automatically handle this complexity is a big
benefit. This design has a multi-rate datapath with a system interface
running at yet another rate (total of six clock domains). The Synphony
C model effectively models the multi-rate design and even exploits it
for higher performance, as shown below.The design is simulated for one million input samples in the associated testbench. The simulation times are shown in the following table. Significant performance improvements over Simulink and RTL simulation are realized using the C model even though cycle accuracy is maintained.
Hardware models with the right combination of accuracy and simulation performance can accelerate integration and system verification tasks -- if they are available early enough in the design flow. With the right balance of performance, accuracy, and flexibility, automatic C-model generation tools such as Synphony Model Compiler can achieve significant simulation speedup and eliminate the hardware model availability problem. Furthermore, the availability of these models can shorten integrated verification and system validation cycle by weeks or months compared to traditional methods.
For more information about Synopsys’ Synphony Model Compiler, please click here.
About the author
Chris Eddington is Sr. Technical Marketing Manager for High-Level Synthesis at Synopsys and has over 20 years of experience in ASIC and FPGA design. He has held various roles in technical marketing, algorithm development and IC design at semiconductor companies doing video and audio conferencing ICs and wireless communications systems. He holds an MS engineering degree from the University of Southern California and an undergraduate degree in Physics and Math from Principia College.
If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you).
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