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Formal methods for power-aware verification
Lawrence Loh
12/17/2012 10:42 AM EST
How to apply formal methods
Formal methods are used throughout the design flow from architectural validation, through RTL implementation, to post-silicon debug — and this applies to power-aware verification, too (see figure 2).
The question is: what is the optimum approach for applying formal methods to power-aware verification? The traditional approach to using formal technology is to license a general purpose, all-in-one formal verification tool suite and acquire the broad and deep expertise to use it. However, many teams want to apply formal to only a subset of the verification challenges, then expand their formal capabilities later as the challenges expand and diversify [3].
The “apps” approach to formal verification supports this need [4]. An app targets an individual formal verification application. It provides all of the tool functionality and formal methodology necessary to perform its intended application-specific task, such as architectural validation and clock domain verification. This approach requires the user to acquire only the expertise necessary for the particular task at hand. JasperGold Apps can be applied throughout the power-aware verification flow, enabling the team to apply formal methods only as needed, and at a pace that suits the team’s project requirements and expertise.
That’s how you apply formal methods to power-aware verification.
About the author
Lawrence
Loh is vice president of Worldwide Applications Engineering at Jasper
Design Automation. Loh has been with Jasper for nine years. Prior
experience includes verification and emulation engineering for MIPS, and
Verification Manager for Infineon’s successful LAN Business Unit. Loh
is a graduate of California Polytechnic State University (BSEE) and San
Diego State for his MSEE. He holds four U.S. Patents on formal
technologies.
References
[1] P1801 - Standard for Design and Verification of Low Power Integrated Circuits. IEEE.
[2] Si2 Common Power Format Specification (CPF)
[3] We need a simpler and faster approach to formal verification by Rajeev Ranjan. EE Times.
[4] Interoperable Application-Specific Solutions for Formal Verification Throughout the Design Flow. Jasper Design Automation.
If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you).
Formal methods are used throughout the design flow from architectural validation, through RTL implementation, to post-silicon debug — and this applies to power-aware verification, too (see figure 2).
The question is: what is the optimum approach for applying formal methods to power-aware verification? The traditional approach to using formal technology is to license a general purpose, all-in-one formal verification tool suite and acquire the broad and deep expertise to use it. However, many teams want to apply formal to only a subset of the verification challenges, then expand their formal capabilities later as the challenges expand and diversify [3].
Figure 2: Formal methods in power-aware verification
The “apps” approach to formal verification supports this need [4]. An app targets an individual formal verification application. It provides all of the tool functionality and formal methodology necessary to perform its intended application-specific task, such as architectural validation and clock domain verification. This approach requires the user to acquire only the expertise necessary for the particular task at hand. JasperGold Apps can be applied throughout the power-aware verification flow, enabling the team to apply formal methods only as needed, and at a pace that suits the team’s project requirements and expertise.
That’s how you apply formal methods to power-aware verification.
About the author
Lawrence
Loh is vice president of Worldwide Applications Engineering at Jasper
Design Automation. Loh has been with Jasper for nine years. Prior
experience includes verification and emulation engineering for MIPS, and
Verification Manager for Infineon’s successful LAN Business Unit. Loh
is a graduate of California Polytechnic State University (BSEE) and San
Diego State for his MSEE. He holds four U.S. Patents on formal
technologies.References
[1] P1801 - Standard for Design and Verification of Low Power Integrated Circuits. IEEE.
[2] Si2 Common Power Format Specification (CPF)
[3] We need a simpler and faster approach to formal verification by Rajeev Ranjan. EE Times.
[4] Interoperable Application-Specific Solutions for Formal Verification Throughout the Design Flow. Jasper Design Automation.
If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you).
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