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Flexible and novel partitioning strategy for hierarchical design
Gurinder Singh Baghria, Kushagra Khorwal, Naveen Kumar - Freescale
12/27/2012 11:10 AM EST
Case 2
Similarly for case 2, pin placement is on the right, top and bottom side of partition E. There is little to do with the right side. In order to get area form this partition we have to do the same procedure as in partition A but on the left side of partition E. This will result in having some white space towards the left side in partition E, or this can be viewed as virtually shrinking the block from X to X - delta X from the left side.
Once the block-level implementation is done, we utilize the area obtained from blocks for the top level. With this proposed approach, we are not able to directly utilize the area obtained from blocks for top-level congestion resolution. To get this area utilized at the top level without changing top-level placement, some intelligent top-level implementation is needed.
Similarly in case 2. To resolve congestion shift the block towards the left side.
With this approach a significant area becomes available for resolution of the congestion at top level. Once routing congestion gets resolved, at the end DECAPs and FILLERs needs to be placed in the design to maintain the dynamic power stability and N-well continuity. These partitions don’t allow you to place DECAPs and FILLERs in the area which was the buffering channel and now hides below the partition due to its movement because the block has the attribute as “MACRO” but some buffering logic is still place in that area as we do not change top level placement. Non Insertion of FILLERs and DECAPs will create DRC’s for non-continuous NWELL in buffering region. In order to make the buffering channel placeable, partition attribute needs to be changed from “MACRO” to “COVER”. Converting partition form MACRO to COVER cell will also allow the placement of DECAPs and FILLERs below the partition. In order to avoid any top-level placement in the region which is utilized inside the block, the placement blockage needs to be inserted below the partition to replicate the placeable area inside the block, except for the buffering channel (where partition is initially placed before any changes). By following the proposed approach we are able to close the design by virtually shrinking the partition size to resolve the congestion in a less iterative manner.
Conclusion
The proposed approach is a solution for signal routing congestion in hierarchical design at the top level. It involves a new concept of virtual shrinking of the partition dimensions and then closing the sub-partition activities in ECO mode. This reduces cycle time and effort.
About the authors
Gurinder Singh Baghria is working as Design Engineer at Freescale Semiconductor, India Pvt Ltd with more than two years of experience in SOC physical design activities.
Kushagra Khorwal is working with Freescale Semiconductor, Noida, India, as a lead design engineer in the field of SOC physical design.
Naveen Kumar is working as a senior design engineer at Freescale Semiconductor, India Pvt Ltd with more than four years of experience in SOC physical design activities.
If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you).
Similarly for case 2, pin placement is on the right, top and bottom side of partition E. There is little to do with the right side. In order to get area form this partition we have to do the same procedure as in partition A but on the left side of partition E. This will result in having some white space towards the left side in partition E, or this can be viewed as virtually shrinking the block from X to X - delta X from the left side.
Once the block-level implementation is done, we utilize the area obtained from blocks for the top level. With this proposed approach, we are not able to directly utilize the area obtained from blocks for top-level congestion resolution. To get this area utilized at the top level without changing top-level placement, some intelligent top-level implementation is needed.
Figure5: Solution and result with proposed approach
In
case 1 we freed some area from the top side of partition A for the top
level. In order to make the resources available in the congestion
region, which is on the bottom side, partition A needs to be shifted in
an upward direction. By doing so partition A gets overlapped with the
buffering channel between the two adjacent partitions or possibly with
the other partition. Because the partition is empty this won’t create
any DRC’s with the top level or with other partition by performing this
move. Similarly in case 2. To resolve congestion shift the block towards the left side.
With this approach a significant area becomes available for resolution of the congestion at top level. Once routing congestion gets resolved, at the end DECAPs and FILLERs needs to be placed in the design to maintain the dynamic power stability and N-well continuity. These partitions don’t allow you to place DECAPs and FILLERs in the area which was the buffering channel and now hides below the partition due to its movement because the block has the attribute as “MACRO” but some buffering logic is still place in that area as we do not change top level placement. Non Insertion of FILLERs and DECAPs will create DRC’s for non-continuous NWELL in buffering region. In order to make the buffering channel placeable, partition attribute needs to be changed from “MACRO” to “COVER”. Converting partition form MACRO to COVER cell will also allow the placement of DECAPs and FILLERs below the partition. In order to avoid any top-level placement in the region which is utilized inside the block, the placement blockage needs to be inserted below the partition to replicate the placeable area inside the block, except for the buffering channel (where partition is initially placed before any changes). By following the proposed approach we are able to close the design by virtually shrinking the partition size to resolve the congestion in a less iterative manner.
Conclusion
The proposed approach is a solution for signal routing congestion in hierarchical design at the top level. It involves a new concept of virtual shrinking of the partition dimensions and then closing the sub-partition activities in ECO mode. This reduces cycle time and effort.
About the authors
Gurinder Singh Baghria is working as Design Engineer at Freescale Semiconductor, India Pvt Ltd with more than two years of experience in SOC physical design activities.
Kushagra Khorwal is working with Freescale Semiconductor, Noida, India, as a lead design engineer in the field of SOC physical design.
Naveen Kumar is working as a senior design engineer at Freescale Semiconductor, India Pvt Ltd with more than four years of experience in SOC physical design activities.
If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you).
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