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Making ESL power optimization a reality
Shawn McCloud, Bryan Bowyer and Vikas Tyagi - Calypto
1/7/2013 8:00 AM EST
Second case study
Case study #2 Architectural exploration
This test focused on the impact of architectural exploration on reducing power. It provides examples of the effect on power of selecting bit widths during quantization and then demonstrates the automatic power optimizations.
Many design teams have general guidelines used to decide on the bit widths required in a float-to-fixed conversion. However, these guidelines may be wrong because they were developed based on older ASIC technologies and over-simplify the problem of power optimization. The following example shows numerical refinement of a FIR filter running at 400 MHz on a 65 nm technology. The change to the bit width is done by editing the C++ source and entering the technology and clock speeds as constraints to Catapult LP.
The selection of the optimal bit widths depends on the percent error versus floating point, area, and power consumption. Note that the lowest power design is not the smallest and that the percent error does not also correlate with average power consumption.
The optimal bit width depends on the underlying technology and clock speed. For example, here is the same experiment run with a 90 nm technology at 200 MHz. At the 90 nm technology node the FIR with eight register and coefficient bits has about average power consumption, but at 65 nm that solution has the best power and area.
Raising the abstraction level above the RTL provides additional power optimization opportunities. A successful ESL hardware implementation flow should allow the designer to explore architectures for power, produce RTL that is power efficient, and quickly compare different architectural solutions for power usage. Our tests showed that using an HLS tool with a low power option allows designers to produce the lowest-power RTL within a seamless, automated flow.
About the authors
Shawn
McCloud is Vice President of Marketing at Calypto Design Systems.
Previously, he was the Product Line Director for the Mentor Graphics HLS
technology after several years as a senior system architect responsible
for RISC and CISC based micro-processor design. Shawn received his B.S.
degree in electrical and computer engineering from Case Western Reserve
University.
Vikas
Tyagi is Application Engineer at Calypto Design System. Previously he
worked as Technical Marketing Engineer for Mentor Graphics HLS
technology after several years as system architect for SDH systems.
Vikas received M.S. degree in electrical engineering from National
Institute of Technology, Kurukshetra in India.
Bryan
Bowyer leads the Product Design team at Calypto Design Systems. He was
previously the Product Manager for HLS at Mentor Graphics and has
worked on HLS tools for the past 13 years. Bryan received his B.S. in
Computer Engineering from Oregon State University.
If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you).
Case study #2 Architectural exploration
This test focused on the impact of architectural exploration on reducing power. It provides examples of the effect on power of selecting bit widths during quantization and then demonstrates the automatic power optimizations.
Many design teams have general guidelines used to decide on the bit widths required in a float-to-fixed conversion. However, these guidelines may be wrong because they were developed based on older ASIC technologies and over-simplify the problem of power optimization. The following example shows numerical refinement of a FIR filter running at 400 MHz on a 65 nm technology. The change to the bit width is done by editing the C++ source and entering the technology and clock speeds as constraints to Catapult LP.
Table 4: Numerical refinement of a 64 tap FIR filter — 65 nm and 400 MHz
The selection of the optimal bit widths depends on the percent error versus floating point, area, and power consumption. Note that the lowest power design is not the smallest and that the percent error does not also correlate with average power consumption.
The optimal bit width depends on the underlying technology and clock speed. For example, here is the same experiment run with a 90 nm technology at 200 MHz. At the 90 nm technology node the FIR with eight register and coefficient bits has about average power consumption, but at 65 nm that solution has the best power and area.
Table 5: Numerical refinement of a 64 tap FIR filter - 90 nm and 200 MHz
ConclusionRaising the abstraction level above the RTL provides additional power optimization opportunities. A successful ESL hardware implementation flow should allow the designer to explore architectures for power, produce RTL that is power efficient, and quickly compare different architectural solutions for power usage. Our tests showed that using an HLS tool with a low power option allows designers to produce the lowest-power RTL within a seamless, automated flow.
About the authors
Shawn
McCloud is Vice President of Marketing at Calypto Design Systems.
Previously, he was the Product Line Director for the Mentor Graphics HLS
technology after several years as a senior system architect responsible
for RISC and CISC based micro-processor design. Shawn received his B.S.
degree in electrical and computer engineering from Case Western Reserve
University.Vikas
Tyagi is Application Engineer at Calypto Design System. Previously he
worked as Technical Marketing Engineer for Mentor Graphics HLS
technology after several years as system architect for SDH systems.
Vikas received M.S. degree in electrical engineering from National
Institute of Technology, Kurukshetra in India. Bryan
Bowyer leads the Product Design team at Calypto Design Systems. He was
previously the Product Manager for HLS at Mentor Graphics and has
worked on HLS tools for the past 13 years. Bryan received his B.S. in
Computer Engineering from Oregon State University.If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you).
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