Circuit reliability challenges for the automotive industry

There are other circuit reliability concerns that are important for automotive applications, such as electrostatic discharge (ESD) and latch-up checking, and there are many design rules for these issues that address both schematic checking and layout checking [3],[4]. For schematic checking, the rules are directed more towards verifying the presence of the appropriate protection schemes from a topological perspective. Users can perform checks on circuitry directly connected to pads, as well as checks on the ESD network. For layout checking, the rules focus on verifying the point-to-point parasitic resistance between the pad and the ESD device, checking current density between pad and the ESD device, detecting pmos/nmos devices sharing the same well, detecting pmos/nmos field oxide parasitics, detecting latch-up issues, and more. All of these types of verification can be addressed with an advanced circuit reliability verification tool.

Conclusion

Circuit reliability verification for automotive applications is a challenging task, which only increases as the technology advances. Advanced circuit reliability verification tools include specific technologies to make efficient, automated circuit reliability verification practical, helping designers achieve the reliable, accurate, and comprehensive verification necessary to ensure a robust and reliable design.

References

[1]    P. Gibson, F. Pikus, L. Ziyang, S. Srinivasan, “A Framework for Logic-Aware Layout Analysis,” Quality Electronic Design, (ISQED), 2010, 11th International Symposium on, pp. 171-175, 22-24 March 2010
doi:10.1109/ISQED.2010.5450415
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5450415&isnumber=5450389

[2]    K. J. T. K. F. A. A. Kollu, "Unifying design data during verification: Implementing Logic-Driven Layout analysis and debug," in IC Design & Technology (ICICDT), 2012 IEEE International Conference on, pp.1-5, May 30 2012-June 1 2012
doi: 10.1109/ICICDT.2012.6232874
URL:http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6232874&isnumber=6232832

[3]    Muhammad, M.; Gauthier, R.; Junjun Li; Ginawi, A.; Montstream, J.; Mitra, S.; Chatty, K.; Joshi, A.; Henderson, K.; Palmer, N.; Hulse, B.; , "An ESD design automation framework and tool flow for nano-scale CMOS technologies," Electrical Overstress/ Electrostatic Discharge Symposium (EOS/ESD), 2010 32nd , vol., no., pp.1-6, 3-8 Oct. 2010
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5623716&isnumber=5623704

[4]    Mauro Fragnoli, Eleonora Gevinti, Antonio Bogani, Lorenzo Cerati, " Novel initialization and implementation method for HBM ESD compliance automated check on Smart Power IC’s", DAC User-Track, 2012
URL: http://www.dac.com/conference+program+user+track.aspx?event=334&topic=8

About the Author

Dina Medhat is a Senior Technical Marketing Engineer for Calibre Design Solutions at Mentor Graphics. She has been with Mentor Graphics for 7 years in various product and technical marketing roles. Dina holds a BS and an MS from Ain Shames University, Cairo, Egypt. She may be contacted at dina_medhat@mentor.com