Design Article
Stars of DesignCon: Thermal Co-Design Key to 3D Chip Success
R Colin Johnson
1/16/2013 11:55 AM EST
Successful three-dimensional integrated circuits (3D-ICs) use co-design techniques that perform thermal analyses not just of each individual die, but of all the dice in a 3-D die-stack, its packaging, the printed circuit board (PCB) on which the 3-D package is mounted and the enclosure holding all the PCBs in a system.
[Click here to register for DesignCon 2013, Jan. 28-31 at the Santa Clara Convention Center. Options range from an All-Access Pass to Free Expo Admission, which includes the option to attend a dozen tech training sessions.].
"If you do not have co-analysis of thermal performance from the chip all the way to the system, then you are not considering all the variations, all the possibilities for 3D-ICs," said Stephen Pan, senior product specialist at Ansys Inc. (San Jose, Calif.). Pan will be speaking at the DesignCon session Thermal Co-analysis of 3D-IC/Packages/System on Tuesday, Jan. 29 at 11:05 am.
3D-IC designs that are temperature aware, according to Pan, are essential for next-generation stacked dice, since traditional thermal analysis techniques cannot simultaneously consider all the different factors. The main obstacle is that chips, packages, PCBs and systems all use different length scales with dimensions that range over a factor of 10,000--from microns to decimeters--which is too wide a range for a single tool to include all the details.
"However with co-analysis we can bridge this gap between these different scales--that's the value of this kind of co-analysis," said Pan.
Temperature aware 3D-IC designs (left) represent device-layer power on a map of tiles (middle) each of which has its own temperature-dependent leakage profile (right).
Temperature-aware chip designers need to consider all aspects of a chip's, board's and system's thermal performance in order to accurately calculate on-chip signal response. And that requires the use of co-design techniques which can model not only individual die, but how they are affected by adjacent stacked die, how the package handles dissipation, how the PCB transfers heat and how the system exhausts it.
In the past, designers hedged around the requirements of thermal co-design by modeling at the highest permitted temperature, resulting in designs that were too conservative, since in practice the temperature will never simultaneously be at its maximum at all locations in a chip, package, board and system.
"If a chip design is not temperature aware, then some features will have to be based on overly conservative temperatures estimates," said Pan.
However, by calculating a power map that is temperature dependent, co-analysis can be used to reveal chip features that might be affected by thermal analysis, such as limits on electro-migration, IR drop and leakage power update.
Thermal co-design can be applied to a single die, 2.5-D dice on silicon interposers, or full-fledged 3D-IC stacked dice, each with a different temperature dependent power map, but which are analyzed simultaneously.
Info Redux:
Session: Thermal Co-analysis of 3D-IC/Packages/System
DesignCon Registration (direct to registration page link): Click here to register for DesignCon 2013, Jan. 28-31 at the Santa Clara Convention Center. Options range from an All-Access Pass to Free Expo Admission, which includes the option to attend a dozen tech training sessions.
And Don't Miss: DesignCon Free Education & Training
(Host: Agilent Technologies; Corporate Sponsore: Rambus; Diamond Sponsor: SiSoft; Diamond Sponsor: Teledyne LeCroy: Platinum Sponsor: Rohde & Schwarz)
Monday, January 28:
• Challenges and Solutions in Characterizing a 10Gb Device (Agilent)
• PCI Express 3.0 Characterization,Compliance, and Debug for Signal Integrity Engineers (Teledyne LeCroy)
Tuesday, January 29:
• Synchronous Time and Frequency Domain Measurements Using a Digital Oscilloscope (Rohde & Schwarz)
• Ensuring Validation & Analysis of Complex Serial Bus Link Models (Tektronix)
• USB 2.0 Compliance Testing (Rohde & Schwarz)
• Phase Noise and Jitter Measurements (Rohde & Schwarz)
• True Differential S-parameter Measurements / Rohde & Schwarz
• Synchronous Time and Frequency Domain Measurements Using a Digital Oscilloscope (Rohde & Schwarz)
• USB 2.0 Compliance Testing (Rohde & Schwarz)
• Phase Noise and Jitter Measurements (Rohde & Schwarz)
• True Differential S-parameter Measurements (Rohde & Schwarz)
• Ensuring Validation & Analysis of Complex Serial Bus Link Models (Tektronix)
• Advances in 3D SI Simulations of Interconnects for Chip/Package/PCB (CST of America Inc.)
Wednesday, January 30:
• Making DDR4 Work For You (Agilent)
• Debugging to Find the Root Cause of Compliance, Limit or Mask Test Violations (Teledyne LeCroy)
|
|
|
|
|
