Multiple domain analysis
a complex SoC, the design may be partitioned across several FPGAs
running in parallel on the debugging platform. In addition, each FPGA
may have multiple clock domains. A typical ASIC prototype, then, might
have on the order of 20+ clock domains. Such complex systems have the
potential for complex problems. In the past, when issues have spanned
multiple chips and clock domains, engineers have had to trace the
relevant signals separately and then manually piece together the data to
correlate events, a tedious and error-prone process.
addresses the complexity of multi-chip, multi-domain debugging by
automating time correlation. Through the use of integrated analyzer
software, Certus can collect trace data from across the system and align
it in time to provide a system-wide, time-correlated view. In contrast
to the manual approach, the relevant data can be captured with a single
It’s also worth noting that since
Certus works at the RTL-level, it can be used in conjunction with the
CAD flow used for the design. Available software tools
guide engineers through the process of signal selection and
instrumentation and can be fully automated as part of an implementation
flow. Verification can also be automated to enable multiple capture runs
using different instrumentation configurations. This is especially
important for verification and development of software applications,
which are typically developed in parallel to hardware. FPGA-based
prototyping enables hardware and software to be tested together so that
the software is fully tested and available when the silicon ships.
the capability to bring full RTL-level visibility to FPGA-based
prototypes, the Certus ASIC prototyping design platform provides a
single tool that supports accelerated development, verification, and
debugging of ASIC hardware and software. Companies that in the past
considered using an emulator, or accelerator may no longer need to make
that investment. Given the significant cost and performance benefits of
FPGA-based prototypes, it may be time to rethink the traditional views
of both technologies.
Certus can be used with all high-end Xilinx
and Altera FPGAs and all commercially available FPGA prototyping boards
regardless of the specific I/O or FPGA topology. Though a standard JTAG
interface, Certus requires no special I/O or connectors to achieve
fully synchronized debugging across multiple FPGAs and clock domains.
About the author
Brad Quinton is the Chief Architect for the Tektronix Embedded Instrumentation Group. He can be reached a email@example.com.
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