Signal EM flow overview
IC Compiler EM Flow (Fig 7 below) reads in EM constraints from the
vendor library (Synopsys plib or IEEE 1603 ALF format) along with
switching activity information (SAIF / Tcl). There is a prevention flow
for clock nets where user provided cell-based NDRs are applied during
clock tree synthesis and honored during routing. The signal EM analysis
and fixing flow is enabled via a single command and should be performed
after route optimization on a timing /route DRC clean database.
automatic EM fixing flow in IC Compiler uses both route and cell-based
techniques such as segment sizing on wires/vias, net based NDRs and
timing- aware cell sizing. Additional flexibility is provided through
user control to select a specific technique based on design
characteristics to further minimize impact to timing/DRC.
Figure 7: [IC Compiler Signal EM Flow], Source: Synopsys
importantly, IC Compiler’s EM analysis is well correlated to HSPICE,
offering an accurate and convergent solution for today’s challenging
Altera’s experience using IC Compiler EM solution
in Altera’s headquarters in San Jose, Calif., the physical design
engineering team managed by James Deng supports multiple RTL front-end
teams for netlist to GDSII support and helps define implementation
methodology for their high-performance designs. The team was chartered
with implementing all the RTL-based IP and subsystem in Altera’s first
high-performance 28-nm FPGA (Stratix V). In order to ensure that the
reliability of their device was not compromised, the team decided to
perform signal EM analysis for the first time ever and chose to use IC
Design details and challenges
targeted for signal EM analysis was a PCI IP, which had a hierarchical
implementation with 11 sub blocks partitioned for IP re-use (Fig 8)
operating at 500+ Mhz.
Figure 8: [Altera's 28nm PCI IP Floorplan], Source: Altera
the programmable IP had many functional modes and complex clock
structures, MCMM-aware EM analysis was a must. The high aspect ratio of
certain blocks also made them prone to routing congestion, which meant a
conservative approach to EM fixing was not viable.
Altera’s EM flow
prevent excessive EM violations post route, Altera chose to use NDRs on
clock nets during CTS and followed with IC Compiler’s signal EM
analysis and fixing flow after routing. Different MCMM scenarios were
created for EM analysis in order to achieve the most comprehensive
coverage. The segment-based fixing approach in IC Compiler was selected
due to the high routing congestion in the design.