Addressing signal electromigration (EM) in today’s complex digital designs

Results

IC Compiler’s automatic signal EM flow was able to fix the majority of the violations with minimal DRC impact. Shown below (Fig 9) are results from two of the PCI IP blocks.

A few violations were left unfixed due to congestion and were later addressed manually by designers.

Altera also found IC Compiler’s GUI features very useful and intuitive to view the EM current density maps and understand the hot spots in the design (Fig 10).  

Furthermore, the report files provided clear and detailed information, making it simpler for the first-time user to comprehend the data (Fig 11).


Altera successfully ran IC Compiler’s signal EM flow on all the blocks in their first 28-nm FPGA chip and has now deployed it as part of their production flow.

Altera’s Design Engineering Manager, James Deng had this to say based on their experience - “We found that IC Compiler’s signal EM flow provided an easy solution with clear reporting and automatic fixing methodology. The MCMM feature in Signal EM was very useful to us. It reduced the risk of merging scenarios ad avoided pessimistic/optimistic analysis. We recommend using IC Compiler to check and clean all signal EM violations before signoff”.

Conclusion
At 28 nm and beyond, geometry scaling and higher frequencies have made EM failures not just a possibility but a reality for every design.  Signal EM analysis has become an integral part of physical design methodology.  As experienced by Altera, IC Compiler provides an easy-to-use, accurate and comprehensive EM solution that addresses the needs of today’s complex and challenging designs.

Acknowledgements
The authors would like to acknowledge the invaluable efforts of their colleagues, Kevin Huang at Altera and Rajiv Dave at Synopsys, who have helped in providing the data for this article.

About the authors
Geetha Rangarajan is a senior technical marketing manager for IC Compiler at Synopsys. She has over 15 years of experience in the ASIC and semiconductor industry. Prior to Synopsys, she worked at LSI as an ASIC design engineer focusing on place and route, design for test and static timing analysis for several key networking and storage designs. Before that, she worked at Texas Instruments on the library characterization team. Rangarajan holds a bachelor of engineering degree in electronics and communication engineering from Coimbatore, India.

James Deng is the physical design engineering manager at Altera. He is responsible for developing ASIC-style physical design solutions, and implementation of high performance digital IPs at cutting-edge technology node. He has over 16 years of experience in ASIC/SoC/FPGA semiconductor industry.  Before joining Altera, he worked at Bay Microsystem on network processor (NPU) design and verification.  He also worked at LSI Logic as senior ASIC design engineer developing advanced ASICs from RTL to GDS.  James holds MSEE degree in VLSI circuit design and computer engineer area from Purdue University and a BE degree from Tsinghua University in China.

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