Design Article
Comment
chipmonk
In order to gain credibilty this group would have to publish technical details - ...
docdivakar
Nice move, the open ecosystem part is appealing; how ever, is there a clearly ...
UMC, Stats ChipPac team for 3-D IC demo
Peter Clarke
1/29/2013 8:48 AM EST
LONDON – Chip packager Stats ChipPac Ltd. and foundry United Microelectronics Corp. have demonstrated a 3-D stacked chip made using through-silicon vias (TSVs) and developed under an open ecosystem collaboration.
The 3-D chip stack comprises a Wide I/O memory test chip stacked on top of a 28-nm processor test chip with embedded TSVs. Stats ChipPac and UMC did not reveal the processor type or the source of the Wide I/O die.
Under the 3D-IC development project with Stats ChipPac, UMC provided the front-end of line wafer manufacturing with a 28-nm polysilicon silicon oxynitride gated process that includes TSVs.
The know-how developed will be applied for implementation on the foundry's 28-nm high-K metal gate (HKMG) process, the companies said. For MEOL and BEOL, Stats ChipPac performs the wafer thinning, wafer backside integration, copper pillar bumping and chip-to-chip 3-D stacking.
"We see no imperative to restrict 3-D IC to a captive business model, as UMC's development work with nearly all the major OSAT [outsourced semiconductor assembly and test] partners for 3-D IC has been very productive. Our successful collaboration with a leading OSAT partner like STATS ChipPAC has further established the viability of an open ecosystem approach," said S.C. Chien, vice president of Advanced Technology Development at UMC, in a statement issued by Stats ChipPac.
Related links and articles:
www.umc.com
www.statschippac.com
News articles:
DesignCon: Cisco packs silicon photonics on 3-D ICs
UMC, Singapore's IME team on TSV process for image sensors
Stats ChipPac re-appoints former ST boss as director
|
|
|
|
|
Navigate to related information
chipmonk
1/29/2013 11:41 AM EST
Since TSMC rather aggressively staked out their claim to the whole process flow for TSV based 3-D stacking, the liliputs have been forming consortia.
More power to them.
But 3D is not yet a mature technology ( immature process steps e,g. high aspect ratio fille TSVs, bond / debond, OR unresolved performance issues: stress and heat related effects on devices in the inner layers ).
Its implementation into products, like any new technology will start at the high end ( military, medical implants ),not with Smart Phones, perhaps not even Servers as some Boosters have been promising for a few years.
At present much of the hot air is coming from Govt. funded European Research Labs. They do not have an enviable record in Microelectronics.
Sign in to Reply
resistion
1/29/2013 8:13 PM EST
I worry that the TSV trend will favor the more (only?) vertically integrated electronics company, i.e., Samsung, since there is no standards barrier for them.
Sign in to Reply
pica
1/30/2013 4:30 AM EST
Heat is even a problem in 2D designs. How do 2.5D or 3D designs deal with heat?
Sign in to Reply
resistion
1/30/2013 6:29 AM EST
Depends on thermal resistance of the interposer.
Sign in to Reply
pica
1/30/2013 8:11 AM EST
But independent of the thermal resistance of the interposer the heat surface ratio get worse.
One idea to deal with that problem to significally frequncies and over-compensate this with massiv paralellism. As a simple example instead of transmitting 256bit@2GHz, transmit 4Kbit@0.5GHz. Heat dissipation should almost be the same, but the throughtput increased 4x. I know also latency increases 4x.
Sign in to Reply
Kresearch
1/30/2013 8:31 AM EST
I remembered UMC teamed with PowerTech and Elpida in 3DIC ~2 years ago. Now team with Stats ChipPac. This implied something. @Peter could we get more insight?
Sign in to Reply
docdivakar
1/30/2013 12:00 PM EST
Nice move, the open ecosystem part is appealing; how ever, is there a clearly defined EDA flow or is it going to be a hodgepodge of piecing together a disparate set of tools?
MP Divakar
Sign in to Reply
chipmonk
1/30/2013 4:24 PM EST
In order to gain credibilty this group would have to publish technical details - the sooner the better. What were the bandwidth and power needed to transfer data ? Include construction details and all electrical / functional tests carried out.
Sign in to Reply