DVFS chip shows GloFo bulk CMOS good for low power

LONDON – A test chip developed by a team at the Technische Universitat Dresden has shown that a 28-nm CMOS from Globalfoundries is good for "ultra-low power" system chips, according to a Globalfoundries' executive.

The TU Dresden team realized the dynamic voltage and frequency scaling (DVFS) test chip using a Xtensa LX4 DSP core from Tensilica Inc. ( ) equipped with power management IP from RacyICs GmbH (Radebeul, Germany) implemented in 28nm Super Low Power (SLP) process technology from Globalfoundries Inc.

The chip is able to operate across a voltage range from 0.7-Vto 1.1-V and a clock frequency range from 90-MHz to 1-GHz. Within those bounds the optimal voltage/frequency combination is determined adaptively use of a hardware performance monitor, provided by RacyICs, a startup company offering design and implementation services.

The complete baseline IP for the chip – including standard cell libraries, I/O cells, SRAM blocks and phase locked loop – was developed by the university team, who also did logic synthesis, place and route and sign-off of the test-chip.

"We're very impressed by the high research and engineering competence of the TU Dresden team," said Frank Dresig, European field engineering manager for Globalfoundries. "The chip directly shows the capabilities of our advanced 28-nm SLP process for implementation of ultra low-power SoCs for consumer applications," Dresig added.

The chip has been developed within the scope of project sponsored by the German Federal Ministry of Education and Research (BMBF) within the Cool Silicon cluster.


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