Guidelines for early power analysis

While design sizes and complexities are increasing steadily, the power budget for electronic devices is aggressively decreasing. This increased demand for low power design is driven by various factors. First, wireless devices cannot afford high power consumption due to the limitations of battery power. Second, even wired devices cannot afford high power consumption as the cooling costs are significant. Additionally, in the last few years, government bodies, such as the European Union, have recognized the need for energy efficient devices and have set strict regulations.  So various forces are now compelling the market to produce power-efficient electronic devices.

It is very important for system-on-a-chip (SoC) designers to understand power consumption early in the design cycle to meet the desired power budget. However, one of the complexities involved is that in the initial stages of SoC design not much information is available to accurately estimate power. As the design progresses, power consumption becomes clearer with the availability of simulation vectors, technology libraries and decisions taken for synthesis and routing. On the other hand, the best time to optimize power is in the early stages of the design. The later it gets in the design flow, the harder it gets to make changes to reduce power.  One of the biggest challenges for the designer is to have a set of tools and flows which can work right from the very early stage of the design through the later stages in the flow. This article discusses some of the challenges of setting up such a flow and shares five guidelines for early and accurate power analysis at the register transfer level (RTL) of abstraction. The RTL abstraction for an SoC is developed during the early stages.

Guideline 1: Leverage design activity information

One of the required pieces of information needed for any power analysis tool is the toggle, or activity information of the design. Simulation output files, like VCD and FSDB, contain detailed information of the switching activity of each net in the design. This is known as vector-based power estimation. Estimating power using this kind of information is very accurate but is time consuming.

On the other hand, vector-less power estimation is an approach to estimate the power based on probabilistic toggling information. This approach is much faster but can be also less accurate. Several case studies are available to explain why probabilistic power estimation can be inaccurate, primarily because of   loss in spatial and temporal correlation between the signals. This is however not just related to the signals.

Consider that you are estimating the power of a memory and have the activity and duty cycles for each net connected to the memory. In the technology libraries, the power table for the memory is described as follows:

The power for the memory varies significantly based on the different “when” conditions in the library model. So even if we get an accurate toggle rate and duty cycle of all the nets in the design, no simulation output will provide the duty cycle of these “when” conditions. This is because these “when” conditions are not present as nets in the design. So even if you have a very detailed VCD file for the design, to accurately calculate power, the power analysis needs to do an internal cycle-based simulation.