Guidelines for early power analysis

Guideline 2: Learn from an existing netlist design and apply it to the new RTL.

One of the key benefits of RTL power estimation is to get the power analysis early in the cycle. The flow does not go through the complete back-end steps. However, a good power analysis flow should be able to capture the intent of back-end analysis and apply it to the RTL. Scavenging an existing prototype design netlist can provide good information to RTL analysis tools for accurate power estimation as shown in Figure 2.

Many designs these days are derivative designs using the same technology node and libraries. In these cases, parts of the design have already gone through back-end place and route. So when we create a new design using exiting blocks, the early power analysis flow should be able to capture characteristics like capacitance, cell distribution, VT-mix, clock tree buffers, etc. It is important to support a completely automated flow of scavenging the key attributes from the netlist and apply them in RTL power estimation. At the same time, the flow should provide the flexibility for an advanced user to fine-tune the scavenged data.

Figure 2: Scavenging existing technology netlist for accurate RTL power analysis

The following factors affect components of power in the early analysis flow and relevant useful data can be brought into the RTL power estimation for new designs based on an existing netlist with the same technology nodes and libraries:

1. The synthesis engine should be fast enough but relatively accurate to match the area characteristics of actual implementation tools. Synthesis will have to use scan cells, as the final power correlation is being done with scanned netlist design.
2. In general, power analysis tools use minimum area-based cell mapping and may use cells that have very low drive strengths, and therefore this may result in power discrepancies. To work around this problem, use “don’t_use” or “don’t_touch” synthesis constraints on cells that have low drive strengths.
3. The power analysis tool needs to account for the impact of clock buffers added to clock trees and other buffers added to high-fanout nets.
4. In a few cases, libraries might have multiple power rails or blocks in the design that are in switched off power domains. In some cases, you may have different libraries that are operating at different voltages.
5. Clock power depends on the way clock gating is done in the design. By default, clock gating is not done in an early power analysis tool and the flow needs to infer an existing clock gating threshold.