Digital Data Locked Loops – Part 1

The design article comes from the book Practical Applications in Digital Signal Processing by Richard Newbold and will be presented in several parts. The book is published by Prentice Hall and is a massive 1152 pages. An outline of the book including preface and chapter descriptions is provided here. Available in both print and eBook formats. See the Prentice Hall site for more information or from Amazon.

Chapter 11 Digital Data Locked Loops

In previous chapters of the book Practical Applications in Digital Signal Processing, elastic store memories were utilized to reclock asynchronous input tributary bit streams prior to being multiplexed into a synchronous output tributary. We utilized two levels of telephone multiplex signals to demonstrate the use of the elastic store memory. Specifically we used elastic store memories to multiplex two asynchronous DS-1 bit streams into a single DS-1C bit stream. Each of the input bit streams were associated with their own independent bit clock and were asynchronous to one another. Once the lower level bit streams are multiplexed into a higher level bit stream, all clock information associated with the lower level streams is essentially lost. The problem we have now is, how can we reverse this multiplex (i.e., how can we demultiplex the two DS-1 streams and synthesize a bit clock for each stream that is on average identical to its original clock)? The DS-1/DS-1C example is only one of an infinite number of possible examples. The same question can be asked of any demultiplex processing where the multiplexed tributaries were originally asynchronous to one another.

The answer to these questions is to utilize a digital data locked loop (DLL). The DLL is fairly simple device that uses an elastic store memory to synthesize a bit stream clock and then synchronizes the demultiplexed bit stream with that clock. All this takes place with no prior knowledge of the original clock frequency.

DLLs are suited for many applications. In order to maintain continuity within this book, we will describe and design a DLL that can be used to demultiplex the DS-1C tributary that we discussed in detail in Chapter 10, “Elastic Store Memory.” There is no reason, however, to restrict the usage of a DLL to only telephony applications. The DLL we describe in this chapter can be considered a base model that with a few modifications can be used for many other applications as well.

11.1   Digital Data Locked Design

To help us better understand the design of the DLL, we need to have an overall picture of the type of signals and the functional path of the signals we will be processing. For this reason we will utilize the DLL in a simple bit stream demultiplexer to synthesize a bit clock and resynchronize the recovered bit stream.

The functional blocks of a demultiplexer are illustrated in Figure 11.1. This book is only concerned with the shaded blocks in this figure. These blocks are the ones that utilize the DLL to synthesize and resync the recovered bit streams.

It is not the intention of this book to discuss all the other processing that goes on within a demultiplexer, but we will need to briefly describe the format of the demultiplexed signals that serve as inputs to the DLL. For this reason, we will briefly explain the end-to-end signal flow. The tributary demultiplex block receives the high-level multiplex input bit stream and then demultiplexes the bit streams associated with each tributary. At the output of the tributary demultiplex, the bit stream is accompanied by a gated clock that is used to indicate the existence of a valid tributary bit. You can envision the gated clock as the high rate input clock with missing teeth.

Figure 11.1   Simplified demultiplexer block diagram

As shown in Figure 11.1, the clock teeth are present whenever a new information bit is recovered by the demultiplexer. Clock teeth are missing whenever the demultiplexer is off processing an overhead bit or when it is off processing a bit from another embedded tributary, and the corresponding bit periods shrink and expand accordingly. Clearly this is not the desired format and timing of a recovered bit stream that we would like to hand off to any external processors. Instead, we would rather synthesize a valid 50% duty cycle bit clock and then synchronize the recovered bit stream to this clock.

We will use this chapter to design a DLL architecture that is relevant to a real-world digital signal processing (DSP) application. Since the reader is already familiar with the real-world DS-1 and DS-1C signals from the previous chapter, we will use these signals as the input and output of our DLL based demultiplexer.

The input to the demultiplexer is a DS-1C, which carries two DS-1 tributaries. The tributary demultiplex block in Figure 11.1 outputs the gated clock version of both tributaries. The block diagram shows that we select only one tributary for further processing. This will be sufficient for our discussion and development of the DLL architecture. Enhancing this design to process multiple bit streams is straightforward.

The selected bit stream and associated gated clock are fed to the DLL block, where the loop synthesizes a bit clock from the input bit stream and uses this clock to strobe the bit stream out of the DLL. The time aligned and newly formatted bit stream and 50% duty cycle bit clock output from the DLL circuit are illustrated in Figure 11.1.

The reader should remember that we have no idea what the frequency of the original tributary bit clock was. All we know is that it must be something within ±77.2 Hz of the 1.544 MHz center frequency, and even then the original clock may have been drifting over time between the two limits. The clock that our DLL synthesizes must on average match the frequency of the original clock, and it should track its drift over time.