Digital Data Locked Loops – Part 1

11.1.1   Digital Data Locked Elastic Store

For those who read the previous chapter on elastic store memories, this section will contain some similar material. However, since the DLL application is significantly different from the bit stream multiplexer application of the preceding chapter, the elastic store memory we use here will be implemented quite a bit differently.

The block diagram of the modified elastic store for the DLL application is illustrated in Figure 11.2. For this application, we are using a 1024-by-1 bit, two-port memory. The logic behind selecting a memory 1024 bits in length will be made clear in later sections. It is enough to say here that we need a 10-bit address space in order to synthesize an accurate and stable DS-1 bit stream clock. We will delve deeper into the reasoning behind this as we proceed with the design.

Figure 11.2   DLL elastic store memory

Figure 11.2 shows a single 1024-by-1 bit, two-port memory. The two-port memory might be a discrete device manufactured by one of the many IC houses. It might also be a macro obtained from a field programmable gate array (FPGA) development software library, or it could have been designed by you, the engineer, using a hardware development language such as VHDL. (VHDL is an acronym for VHSIC hardware description language. VHSIC is an acronym for very high speed integrated circuits.)

No matter what the source, there are a great many methods that can be used to implement a dual port memory of this size. For our purposes, we have chosen to implement a two-port memory using the VHDL design language. This allows us the freedom to design our own architecture and define how the device operates. In this case we have designed a clock synchronous two-port memory. The term synchronous means that a data bit applied to the input data port D1 will be stored into memory at the address applied to port A1 on the leading edge of the clock presented at port W1. Similarly, a bit stored at the address applied to port A2 will be read from memory on the leading edge of the clock applied to port R2. The bit read from memory will appear at the output port D2.

The operation of our custom two-port memory isn’t too much different from common standalone devices available from most memory manufacturers. However since we custom designed the memory ourselves using VHDL inside a programmable logic device, it fits our application perfectly and therefore provides us with our most efficient implementation. In addition, it allows us the flexibility to quickly and easily modify the size of the two-port memory. The importance of this will be shown in later sections.

Operationally, the recovered DS-1 bit stream is applied to the data pin D1 of memory port 1. The gated DS1-C bit clock is applied to the synchronous clock pin W1 of memory port 1. The bit applied to pin D1 will be written in to memory at the address applied to port A1 on the low to high transition of the gated clock. The reclocked DS-1 bit stream is output from the pin D2 of memory port 2. The synthesized DS-1 tributary clock is applied to the synchronous memory read port R2. Data stored at the address applied to port A2 will appear on pin D2 on the leading edge of the synthesized clock. For now the synthesized clock applied to memory port 2 pin R2 seems to mysteriously appear from out of the blue. We will spend much of this chapter discussing the derivation of this clock.

11.1.2   Digital Data Locked Elastic Store Write and Read Pointers

In Figure 11.3 we have added a modulo 1024 counter on both sides of the two-port memory, as indicated by the shaded boxes. These are write and read counters and are clocked with the write clock and synthesized read clock, respectively. The output of the counters are applied to the memory address ports and serve as the write port and read port memory address sources.

We can see from the figure that each time a recovered bit is clocked into memory port D1, the port 1 address is advanced by 1 and it points to the location in memory where the next recovered bit will be stored. The address counter is modulo 1024, so the writing of recovered bits progresses around a 1024-bit circle where the oldest bit stored is written over by the newest bit to arrive. The write address is referred to as a write pointer.

Similarly, each time a synthesized read clock strobes a bit from memory, the read address is incremented by one and it points to the address of the next bit waiting to be read. The read address counter is also modulo 1024, so the reading of data bits progresses around the same 1024-bit circle. The read address is referred to as a read pointer. We can envision the read pointer continuously chasing the write pointer around the circular memory.

The 10-bit write-and-read addresses also serve as 10-bit pointers that are used to calculate the fill difference in the memory. The fill difference is the difference between the write pointer (wPtr *) and the read pointer (rPtr *) and is a measure of how many unread bits are stored in memory. There is no hard and fast rule as to the number of bits needed for each pointer. The criteria for selecting the pointer bit width are based on the desired frequency precision, frequency jitter, and response time of the synthesized DLL read clock. As we will see later, the performance of the synthesized bit clock frequency diminishes as the bit width of the pointers decreases.

Figure 11.3   DLL write and read pointers

Now that we have created a write pointer and a read pointer, we need to compute the number of unread bits in memory. The number of residue bits is computed by subtracting the read pointer from the write pointer. The result is termed the fill difference and given by wPtr * −rPtr *.

This computation is illustrated in Figure 11.4. The adder shown as a shaded block in the figure is 10 bits wide and performs the modulo 1024 pointer subtraction.

To briefly summarize, the two 10-bit modulo 1024 counters provide the port addresses to the dual port memory, and they also provide address pointers that are used to compute the number of unread bits stored in the memory. The number of unread bits is termed the fill difference in the memory.

The reader should note that since the write pointer wPtr∗ and the read pointer rPtr∗ are asynchronous to one another, the period of the fill difference measurement will not be a fixed constant. As a matter of fact, the period of the fill difference measurement will breathe as the two pointers are chasing one another around the circular memory address space. This should be of no consequence for most applications.

Figure 11.4   DLL fill difference calculation

The graphical description of the write and read pointers and the difference between them is illustrated in Figure 11.5. The figure shows a 1024-bit circular memory with a write pointer (wPtr *) and a read pointer (rPtr *) chasing one another around the circle, with each pointer moving at its own rate. The write and read pointers can be visualized as moving around the circular memory with angular velocities determined by their instantaneous clock rate. Thus we can state

wPtr * (ω) = {gated} 3.154 MHz ± 30 ppm

rPtr * (ω) = {synthesized} 1.544 MHz ± 50 ppm

Figure 11.5   DLL modulo 1024­bit circular memory

The angular velocity of the write pointer is expressed as the gated frequency of the base DS-1C bit clock. The write pointer clock is just the input 3.154 MHz ± 30 ppm clock with missing teeth. The gated clock teeth correspond to the occurrence of a demultiplexed tributary bit. Teeth that correspond to the occurrence of overhead bits or to the bits from the second tributary are removed.

So the write clock does not have a 50% duty cycle, and as illustrated in Figure 11.1, the period of each data bit is stretched whenever the demultiplexer is processing overhead bits or bits from the other tributary bit stream. Although the write pointer clock is not pretty, in a pure sense its clock tooth frequency will be equal to the original bit stream clock and will take on a value within the 1.544 MHz ± 50 ppm range of the original bit stream. Believe it or not, many demultiplex designs today treat the recovered but nonuniform bit stream and the random missing tooth clock as an acceptable design architecture. As we will see, we can use the DLL to make a significant performance improvement to this type of design.

The read pointer is the synthesized DS-1 output tributary clock, and it will be a 50% duty cycle clock with an angular velocity within the 1.544 MHz ± 50 ppm range of frequency specified by the International Telephone and Telegraph Consultative Committee (CCITT), known since 1992 as the International Telecommunications Union (ITU), based in Geneva, Switzerland.

When we compute the value for the fill difference, we use circular math or in this case modulo 1024 two’s complement arithmetic. Let’s do some pointer arithmetic so we can get a feel for how the modulo 1024 arithmetic works. When performing modulo 1024 pointer arithmetic, we will adhere to the following three rules:

• We will perform the wPtr * −rPtr * subtraction using two’s complement arithmetic.
• We will ignore any carry bits.
• We will treat the result as a normal unsigned binary number.