Digital Data Locked Loops – Part 1

11.1.4    Digital Data Locked Analog Error Voltage

The main thrust of the design of the DLL is to synthesize the output bit stream clock so that on average it is equal in frequency to the gated input clock and thus equal in frequency to the original tributary bit clock. Even if the original bit stream clock was suffering from a serious frequency drift, as long as it remained within the ITU-specified frequency range, our synthesized clock should track it correctly.

Now let’s put our error signal to work. For the DLL we are designing, we will apply our error signal to the input of a multiplying D/A converter (MDAC) [4]. This addition to our evolving DLL architecture is shown as the shaded block in Figure 11.8.

A MDAC is a simple device that multiplies a voltage reference VREF by an input digital word to produce an analog output voltage V0. The MDAC is slow by modern day standards because it utilizes a fairly old R-2R ladder D/A architecture [2]. An MDAC was chosen for this architecture simply because it lends itself well to circuit description and helps us succinctly illustrate the derivation of a feedback control voltage.

It should be repeated right up front that the MDAC is inherently slow. For designs that need to operate at blazing speed, the MDAC will definitely be the long pole in the tent. For high-speed DLL applications, the MDAC would be replaced with circuit composed of a high-speed D/A and an analog multiplier built using a couple of operational amplifiers [1].

We can see from the figure that the digital error signal is applied to one input to the MDAC and a fixed voltage reference is applied to the other input. The digital error signal (wPtr∗ − rPtr∗) multiplies the reference voltage V_REF to produce an output voltage V₀.

To better understand the derivation of the feedback error voltage V0, let’s take a look at how an MDAC works. Most MDACs can operate in one of two modes: a unipolar mode or a bipolar mode. A 10-bit MDAC operating in the bipolar mode will generate an analog output voltage according to the input/output relationship illustrated in Table 11.1. This table shows that there are 210 or 1024 specific values of output voltage V₀. The MDAC output voltage ranges from a low of −V_REF (512/512) volts through 0 volts to a high value of +V_REF (511/512) volts. In this mode, the MDAC is initially tuned by setting the digital input word to its center value of 10 0000 0000 and then adjusting the MDAC

bias network until the output voltage is 0 volts.

A 10-bit MDAC, operating in the unipolar mode will generate an analog output voltage according to Table 11.2. From this table, we see that the MDAC output ranges from low value of 0 volts to an almost full scale value of V_REF (1023/1024) volts. For a 10-bit MDAC, we can see that the weight of a least significant bit (LSB) is equal to V_REF )1/1024) volts. In this mode, the MDAC is initially tuned by alternately setting the digital input word to all 0s and adjusting the MDAC bias network for an output of 0 volts and then setting the digital word to all 1s and adjusting the output voltage until it is equal to a value of V_REF ( 1023/1024) volts.

For our DLL design we will opt to use the MDAC unipolar mode. We will apply the 10-bit digital fill difference signal directly to the input port of the MDAC, and we should expect to see the same MDAC input/output relationship as indicated in Table 11.2.

Figure 11.8   DLL error voltage generation

So far we have derived our DLL digital error signal and we have defined a method for converting this to an analog error voltage. In the next paragraph will use this analog error voltage to control the synthesized frequency of a digital clock oscillator.

Table 11.1            MDAC Bipolar Configuration      

Table 11.2            MDAC Unipolar Configuration