Using 3rd party IP in ASIC/SoC design

The IP and Vendor Selection process is the most important step as it is the foundation for the whole design. Taking shortcuts during this process will no doubt increase the chance of failures at later stages. This process encompasses matching the IP requirements as per the design needs, finding the right vendors and making sure that the 3rd party IP serves all the needs required for the particular design.

Also, for the various IP being procured, both compatibility and interoperability need to be insured. For example, in TSMC's 40G process, multiple voltages can be supported for the I/O oxide (1.8, 2.5 and 3.3V). However, not all combinations are supported at this technology node. The selection of different I/O libraries and PHYs needs to take this into account to ensure compatibility of the selected IP. Another example involves DDR PHYs and the associated controllers. Interoperability concerns can exist, especially in cases where the DDR and the PHY are procured from different vendors, as the standard for the interface between them is new and may, to a large extent, still be unproven.

Figure 3: IP aggregation in a design

IP Procurement is the next important step after all the IP and vendors have been finalized for a design. This process includes financial, legal, schedule and various other contracts/agreements and negotiations with the vendors.

One other important aspect of procuring the IP from an external vendor is the assessment of views and models delivered by the vendor, which will be used with the existing ASIC semi-custom/full custom design flow.

There have been efforts by bodies like IP-XACT to standardize the IP. However, due to various EDA flows and tool choices due to historical reasons etc., an IP delivered by multiple IP vendors may not look the same. It might require generation of some auxiliary views like IBIS views for IOs from spice, milkyway databases, and characterization at custom corners for analysis etc., which might not be available from an IP vendor as a default delivery option.

IP Qualification is the third step, which incorporates an exhaustive incoming IP inspection process that helps in finding any issues with the IP very early in the project design cycle. This approach provides lead time for the IP vendor to fix any issues upfront that might otherwise show up in the ASIC tape-out phase of the project. This process is required for the same reason most of these steps are in place; the later a bug or an issue involving IP is caught, the more costly fixing it becomes.

IP inspection encompasses checking the IP within itself and with the other IPs in the ASIC. When checking the IP within itself, it is important to perform checks related to IP compatibility with the technology process node selected in terms of mask layers, gate oxides, etc., with the used design flow.

Checking the contents of IP delivery in terms of views completeness is another area that often gets missed. An agreement with an IP vendor might only cover basic views for the RTL to GDSII flow, but there can be a requirement of specific views like IBIS models for IO libraries to do system-level simulations.

Figure 4:  IP qualification process

These steps might come at additional time and cost. Also, there can be the case of an IP view/model having been generated using a flow from one EDA vendor, where it may not seamlessly work with another. Issues like these have the potential to negatively impact the project if not identified early.

Figure 5:  Relative cost of fixing IP with design cycle

IP Integration is technically the last step in the chain even though it typically runs throughout the program until the tapeout. This step is one of the areas that is constantly evolving and when new IPs/vendors are used in a design this process becomes more tedious.  To tackle this task, various IP checklists and integration reviews should be deployed. These should be updated regularly to ensure all the aspects of integration such as timing, DFT, physical design and package are addressed for each IP. These checklists should carry a lot of know-how from the experience of the other designs in terms of best practices and recommendations based on the silicon performance.

There are various requirements that each IP vendor provides on how to use the IP—should these requirements not be met, successful IP integration may be hampered.  Also, as part of the process, IP vendors should do the final reviews and make sure that it satisfies all the requirements. One area that requires attention when managing multiple IP vendors is the understanding of ESD compliance for the entire chip. IP vendors will guarantee ESD targets only for their individual IPs and will have tested ESD compliance for the IPs only in their own testchip environment. IP integration should incorporate specific ESD reviews and analysis for the various IPs integrated on a design to mitigate this risk during the physical design phase of the project. Overall, with this process, there should be significant savings for the companies in terms of last-minute ECOs and metal re-spins by catching some of the issues very early on in the process.

Summary

Achieving a first-time-right SoC design depends greatly on IP Selection, Procurement, Qualification and Integration processes and methodologies. Ensuring that the IP, as used in the SoC, will ultimately meet all requirements is a highly complex task that requires a dedicated and expert team with an explicit focus and responsibility to this task. At Open-Silicon, we have a dedicated IP Application Engineering team, which is responsible for taking care of the whole process described in this article. Open-Silicon’s IP experts work continuously with customers and IP vendors to make sure all the requirements are met and IPs are successfully integrated in the design.

About the author

Mohit Gupta is an IP manager with Open-Silicon, and is responsible for managing the IP for various networking, telecom, storage and consumer application programs. Prior to joining Open-Silicon, Mohit led teams at Infineon Technologies and ST Microelectronics where he was responsible for IP circuit design, layout design, characterization and quality assurance of IP. Mohit holds a BE Degree in EEC from Thapar University, India and an MS degree in Microelectronics from the Birla Institute of Science and Technology, Pilani, India. He also participated in the Executive Program in International Business Management from Indian Institute of Management, Calcutta, India.