Advanced yield enhancement technique: Lithography friendly design

In the nanoscale era, yield of a design is governed by the manufacturing process that involves pattern dependent effects due to lithography, and various manufacturing issues in addition to the traditional particle contamination. Inability of the complex conditional and recommended Design Rule Checks (DRC) to model the sensitivity of a lithographic process window to the actual features being printed has made designers to comply with Lithography Friendly Design (LFD). This article discusses the LFD flow and describes common printability failures to maximize the yield of the design.

As the technology node is shrinking, the lithography systems are made to work at their maximum resolution limit which may cause lithography imperfections resulting in the degradation of yield and circuit performance. Even after performing detailed DRC, extensive Resolution Enhancement Techniques (RET) and Optical Proximity Correction (OPC) techniques to compensate for the effect of process variations, the layout may contain several hotspots causing manufacturability problems and yield loss. Therefore, it is important to successfully suppress the printability failures by performing lithography process simulation before the design layout is used for manufacturing.

Process variation and process variability bands

With smaller technology nodes, the sensitivity to variability increases. Small changes in the lithography process parameters like dose, focus, or mask bias may change the delay and leakage and can affect design performance. These lithography parameters are briefly discussed below:

Depth of focus

During mask preparation, each layer has a separate mask which has to be aligned accurately with respect to the other layers. Each layer has a finite thickness so during lithography it is required that the actual thickness of the layer be reflected while printing the pattern on the silicon. Depth of focus is the parameter which defines how accurately the thickness of the layers is reflected while printing the pattern onto silicon. The greater the depth of focus, the better will be the alignment between the masks.

Dose

During lithography, when the silicon is exposed to the light through the mask, the applied positive photoresist becomes more soluble in the developer solution. In order to completely remove the photoresist from the exposed regions, the exposed resist must absorb a sufficient intensity of light otherwise the exposed resist wont be completely removed in the developer solution and will leave some resist in those regions. Also there may be variations in the intensity of light in various regions of the wafer. This will result in printing imperfections and therefore poor yield and circuit performance.

Mask bias variations

These are mainly introduced during the manufacturing of the mask itself.

The silicon printed images are simulated for variations in the process parameters discussed above and a contour is obtained. A Process Variation (PV) band is the representation of the possible simulated contours obtained by the variations in the process parameters. Several contours combined together make a PV-band. PV-bands show how much and where a design will vary in response to process variations. Each PV-band represents all possible printing locations resulting from one set of dose, focus, mask bias, resist, and etch variation conditions. Figure 1 represents a typical process variation band for a set process parameters which are dose and focus.

Figure 1: Process variation band