Digital Data Locked Loops – Part 2

11.4.2   DLL Simulation Case I => B = 10 bits, k = 0.3016 Hz/bit

11.4.2.1    Input Bit Clock Frequency Swings ±50 ppm

We spent a great amount of time designing a DLL with a 1024-bit elastic store memory and a 10-bit digital error signal, so we will observe the simulation results of that circuit first.

The simulation plot in Figure 11.16 shows the DLL synthesized frequency response to a step in frequency by the input bit clock of +50 ppm or +77.2 Hz above the center frequency, followed some time later by another frequency step of −100 ppm down to −77.2 Hz below center frequency.

Figure 11.16   B = 10 frequency deviation = ±50 ppm

The distance between minor tick marks on the time axis is the equivalent of 106 input bit clock periods. The distance between major tick marks is the equivalent of 10 ^. 10⁶ input bit clock periods. The thick line is the plot of the synthesized VCXO clock frequency f_S (t), and the thin line is the value of the loop error voltage V_O (t ). The values of the DLL circuit parameters listed to the right of the plot are frozen at the time the plot is stopped and represent the latest parameter measurements. These measurements correspond to the last plotted point, which is the last point on the right-hand side of the plot window.

The positive and negative frequency step of the input bit clock is shown as a dashed line. To avoid clutter on the following plots, this dashed step will not be shown, but the reader can rightfully assume that a step has occurred whenever an exponential response of f_S (t) and V_O (t) is initiated.

So what information can we glean from this graphical simulation? Well, we can immediately see from this plot that the loop response is indeed exponential, just as our derived transient response of Equation 11.16 predicted.

We can also see that after the input bit clock frequency instantaneously experiences a step of +77.2 Hz or +50 ppm, the DLL exponentially tracks and eventually locks to the input clock frequency. We can also see that when the input bit clock frequency experiences a negative step such that it is below the center frequency by 77.2 Hz, the DLL exponentially tracks and locks to the new input clock frequency. This time, the negative step was −2 ^. 77.2 Hz = −154.4 Hz, which corresponds to a negative step of −100 ppm.

At time t = 0, the loop error voltage is set to its center value of 1.5 volts. The error voltage exponentially increases to 2.25 volts in response to the input frequency step of +77.2 Hz or +50 ppm and then exponentially decays to 0.75 volts following the negative tributary clock frequency step of –154.4 Hz or −100 ppm down to 1.544 MHz − 77.2 Hz.

It is interesting to note that the plot of both the synthesized bit clock frequency f_S (t) curve and the VCXO control voltage V_O (t) curve pass through the horizontal axis at the same point. This is as it should be, since the time axis is positioned at both the loop center frequency of 1.544 MHz and at the midpoint of the control voltage of 1.5 volts. Remember that when a 1.5 volt error signal is applied to the VCXO, it will synthesize the loop center frequency. So it is good to know that the hardware bit-level simulation behaves correctly in this regard.

We can also see from the parameter measurement list on the right-hand side of the plot that the value of the loop time constant was measured to be k = 0.3018 Hz/bit. As shown in Table 11.4, this value for k is well within 0.1% of the calculated value of k = 0.3016 Hz/bit. The value of k is continuously computed during the 10% to 90% rise/fall time of the response waveform. The accuracy of the computation for k depends on the number of points in the rise or fall time of the curve. A shorter transient response curve will produce less accurate measurements.

The parameter measurement list also shows that when the simulation was stopped, the frequency of the input bit clock (trib offset) is equal to the center frequency –50 ppm and the input bit clock frequency is 1, 543, 922.8 Hz, both of which are expected. In addition we can see from the parameter list that the digital error signal ε_D is equal to 256. The ideal VCXO frequency versus voltage curve of Figure 11.13 says that when the value of the error signal reaches 256, the VCXO output frequency should be 1.544 MHz – 50 ppm or 1, 543, 922.8 Hz and that the VCXO input error voltage should be 0.75 volts. A quick check of the plot measurement list shows that the synthesized frequency F_S does indeed equal 1, 543, 922.8 Hz and the error voltage V_O does indeed equal 0.75 volts.

The parameter list also shows that the difference between the input bit clock and the synthesized bit clock at this particular frequency is clk diff = 0 Hz. This tells us that the loop was able to exactly synthesize this particular frequency. This will only be true when the input frequency exactly equals one of the 1024 discrete frequencies that can be synthesized by this 10-bit DLL.

And finally we do not pay any attention to the “num clks” value in the plot parameter list. That is the number of clocks that have occurred since t = 0. This number is only meaningful during the loop transient response computations. Since the loop is already reached the steady state condition, this number is meaningless.

Now that you are familiar with the format of the simulation plot, let’s view some additional plots to see how the DLL responds to input bit clock frequency steps of different magnitudes.

11.4.2.2    Input Bit Clock Frequency Deviation of +40 ppm

When the DLL was locked to the input bit clock frequency with a deviation of ±50 ppm, we saw that the DLL was able to synthesize a clock frequency that perfectly matched the frequency of the input bit clock. The DLL was able to do this because the digital error signal for those two extreme frequencies just happened to be integer values of 768 and 256. What happens when our DLL cannot synthesize a bit clock frequency that exactly matches the frequency of the input bit clock? Let’s take a look at the case where the deviation of the input bit clock frequency is +40 ppm or +61.76 Hz. The digital error signal that would drive the DLL to synthesize this frequency is calculated by

Since ε_D must be an integer, the closest error values that the loop can compute are the two that bracket 716.7109, which are ε_D = 716 and ε_D = 717. And that is exactly what the DLL will try to do. It will generate an error signal of ε_D = 716 and produce an output frequency f_S1 that is slightly less than the frequency of the input bit clock F_I. Slowly over time the small positive difference between the input bit clock frequency and the synthesized bit clock frequency (F_I − f_S1) will accumulate until the error signal eventually increases by 1 bit to ε_D = 717. The extra error bit will cause the DLL to synthesize a higher output frequency f_S2 that is 0.3016 Hz greater than f_S1 and is a slightly greater than the frequency of the input bit clock F_I. Slowly over time the small negative difference between the input bit clock frequency and the synthesized bit clock frequency (F _I − f_S2) will cause the error accumulation to decay until the error signal eventually decreases by 1 bit back to ε_D =716. This process will repeat itself forever.

The switching back and forth between two synthesized frequencies that closely bracket the target frequency gives rise to synthesized clock jitter. The magnitude and the frequency of the jitter are dependent on the frequency resolution of the loop. The smaller the time constant k, the better the resolution and the smaller the jitter, both in magnitude and frequency. The jitter magnitude is smaller because the difference between the synthesized and tar-get frequency is smaller, and the jitter frequency is smaller because it takes longer for the digital error to accumulate or decay by 1 LSB. The opposite is true if the value of k gets larger. In this case, the resolution decreases and the magnitude and frequency of the synthesized frequency jitter increases.

Let’s verify this by looking at the simulator plot for our design for the case where B equals 10 and the calculated value for our loop time constant k = 0.3016. The plot of the synthesized frequency is illustrated in Figure 11.17. The parameter measurements on the right side of the plot show a post transient response clock difference of (F _I − f_S1 ) equal to –0.06 Hz. We can also see that the value for the digital error is ε_D = 717 . The frequency resolution for our B = 10 bit design is good enough that we can barely see any jitter in the plot of the output frequency. In the plot window, an arrow points to a box that encloses the portion of the plot where the synthesized frequency is actually 0.06 Hz greater than the target input bit clock frequency.

Now take a look at Figure 11.18. Here the error has decayed to the point where the digital error signal ε_D = 716. Now the difference between the input bit clock frequency and the synthesized clock frequency (F_I − f_S2) is equal to 0.24 Hz. Once again there is an arrow in the plot window that points to the box that encloses the portion of the plot where this 0.24 Hz discrepancy occurs. This oscillation between F_I − 0.24 Hz ≤ fS ≤ F_I = 0.06 Hz will continue for forever and is the jitter about the center of the desired synthesized frequency. Figure 11.17 shows that the jitter period is measured to be approximately 20.59 seconds. The jitter frequency is 0.05 Hz and the jitter magnitude is equal to (0.06 + 0.24)Hz = 0.30 Hz. This also is the value for our loop time constant k. It shouldn’t be a surprise that k is also the value of the loop jitter. The loop error signal oscillating between two adjacent levels of ε_D and k is equal to the frequency difference between these adjacent values.

Figure 11.17   B = 10; frequency deviation = +40 ppm (1)

So this little constant k has just taken on another huge role in the behavior of the DLL. Let’s see if we can count all the fun things k contributes to the DLL performance:

1. k is the frequency resolution of the DLL.
2. k is the circuit time constant that determines the attack rate of the loop.
3. k is the magnitude of the jitter in the loop synthesized frequency.

It turns out that this constant k is an extremely important player in the performance of our DLL. The jitter we see for the B = 10 bit case doesn’t sound like a big deal here, but we will show some examples in the next section where this jitter for smaller values of B becomes very pronounced.

One other thing we need to mention here is the rise time of the exponential response. The rise time is defined to be the time required for the curve to rise from 10% to 90% of its final value. The rise time is dependent on the value of k. We will look at the computation of the rise time figure in greater detail when we compare the simulation results with the DLL transient response results we calculate from either of the two expressions presented in Equation 11.16. For now, all we need to know is that the computed rise time for this 10-bit DLL is 7.28 seconds.

Figure 11.18   B = 10; frequency deviation = +40 ppm (2)

We mentioned several times that the clock jitter becomes more pronounced and the transient time of the circuit decreases as the value of the circuit time constant k increases. This makes sense since the units of k are Hz/ bit. As the time constant k gets larger, the frequency resolution decreases, which allows the loop to acquire a step in input frequency more quickly, but because its frequency resolution is decreased, once locked to in input frequency, the loop cannot track with as much precision. The opposite is true when the value of k decreases. The next few simulation cases will demonstrate this very clearly as we take a look at the simulation examples for B = 8, 9, 11, and 12 bits. Once we acquire an understanding of these examples, we will look at some examples of how loop performance degrades when we set B to lower values such as 6 and 7. These two examples are shown primarily to allow the reader to see what problems can arise if loop parameters are not selected with care.

The following are a few things to note about the 10-bit DLL driven by an input clock of 1.544 MHz ± 50 ppm and its response to a ±40 ppm input frequency step:

1. The calculated value of the circuit time constant k is 0.3016.
2. The jitter period is approximately 20.59 seconds.
3. The jitter frequency is approximately 0.0486 Hz.
4. The jitter magnitude is 0.06 + 0.24 = 0.3 Hz, which is equal to k.
5. The exponential rise time is 7.28 seconds.
6. The digital error switches between 716 and 717 bits when tracking the high deviation +50 ppm input.
7. The digital error switches between 307 and 308 bits when tracking the low deviation −50 ppm input.