The Effect of BGA Hole Patterns in Power Planes on High-Speed Signal Quality

Large arrays of clearance holes in power planes can have a dramatic effect on the behavior of high-speed signals. Signal integrity is a growing problem for designers because new designs are calling for components with higher and higher pin counts that must be connected using vias to access the internal layers of printed-circuit boards (PCB). The proper design of the hole and pad stack results in high-yield power planes while preserving the quality of very fast signals routed through these areas. Failure to account for the proper clearances results in low PCB yields due to short circuits, unsatisfactory impedance variations in transmission lines, or both. A typical power-plane structure results when a high-pin-count ball-grid array (BGA) package is mounted on a multilayer PCB.

Figure 1: Illustration of a trace routed over the typical hole pattern created in a power plane by a BGA

Clearance holes in the power planes allow room for the holes drilled through the PCB when creating vias to connect to the BGA pins. The PCB fabrication process used to build the PCB determines the size of the clearance holes. The parameters of a multilayer PCB (A-F in Figure 2) determine its clearance hole.

Figure 2: Anatomy of a drilled, plated hole in a multilayer PCB

The maximum wander of the drilled hole (C in Figure 2) is the sum of the accuracy of the following factors:

• Drill in finding the true hole location
• Ability of the fabrication process to register the inner-layer images
• Registration accuracy of pairs of inner layers
• Amount that inner-layer patterns shift with respect to each other during lamination
• Dimensional stability of the raw materials used to build the PCB
• Amount that the drill may be deflected from the vertical as it passes through the laminate
• Accuracy with which outer-layer images can be registered to inner-layer patterns.

These factors become more important as the PCB size increases. When creating the tolerance budget for a particular PCB design, it is recommended that the panel size to be used in manufacturing be adjusted according to the fabrication specifications.

The dimensions of the plated-through hole in Figure 2 are as follows:

• A = B + two times the plating thickness (normally 1-mil minimum)
• C = A + two times the drill and registration tolerances (usually 6-mils for 18x24" panels)
• D = C + two times the minimum annular ring (usually 2-mils)
• F = D + two times the clearance to nearest copper in plane or signal layers (usually 5-mils)
• For a 12-mil-drilled hole, the clearance hole (F) is 38-mils and the capture pad (D) is 28-mils
• For a 24-mil-drilled hole, the clearance hole (F) is 50-mils and the capture pad (D) is 40-mils.

From this dimensional analysis, we see that the 50-mil-pitch BGAs routed using 12-mil vias resulted in a web of 12-mils, more than enough to preserve the impedance of a 5-mil trace passing over it. This combination of trace width, via size, and clearance pad size results in a buildable PCB that is both electrically sound and easy to fabricate. The clearance pad dimension (F) describes a cylinder that passes through every layer of the PCB. To preserve proper clearances, all copper in every layer must remain outside of this area. Therefore, traces cannot be wider than the web width. If more than one trace is routed between two pins, the combined width and separating space cannot exceed the web width.

In a 1mm or 40-mil-pitch BGA package, the clearance hole for a 12-mil drill still needs to be 38-mils. The remaining web is only 2-mils. Clearly, the impedance of traces passing through an array with these dimensions experiences a significant increase in impedance. More importantly, traces cannot be wider than this 2-mil web to satisfy clearance rules in signal layers.

The current generation of computers and networking equipment frequently uses 1mm BGA packages. To achieve reasonable yields at PCB fabrication, one or more of the dimensions shown in Figure 2 must be decreased. This is often achieved by building PCBs on panels smaller than 18x24". When the PCB size requires the use of 18x24" or larger process panels, 1mm packages cause decreased yields, compromised signal integrity, or both.

Figure 3: Edge Rate Erosion Due to Signal Reflection from Impedance Change in a Typical 1mm BGA Array

Edge erosion on the switching edge is caused by the increase in trace impedance as the signal travels through the BGA array and produces a positive reflection of part of the incident signal. The energy reflected from the impedance change slows down the switching edge. While in most systems this effect can be ignored, the 50psec or higher time delay may be unacceptable for gigabit and above signals.

Remedies for Fine-Pitch BGA Clearance Problems

When 50-mil-pitch BGAs are used, it is possible to choose dimensions that result in uniform trace impedances under the BGA and create a manufacturable PCB. As the pitch of a BGA decreases, the amount of space available to create satisfactory webs and uniform impedance traces diminishes. At 1mm (40-mils), it is possible to achieve the desired result by reducing the size of the PCB panel. In this case, the additional space for a web is gained by reducing the other allowances. As the pitch of a BGA is reduced to below 1mm, such as with uBGAs and chipscale packages, there is not enough copper to preserve the web or provide a good partner for traces routed through the array.

The solution for ball pitches below 1mm is to use a combination of through-hole vias and blind vias. Since the device's power pins need to be connected using through-hole vias, the power-pin assignments on the package are spread out enough to allow adequate webs in the power planes. The signal pins are then routed on signal planes accessed using only blind vias.

Blind vias can be laser drilled to almost any depth, so one might expect to be able to use them to route signals to any buried signal layer. Unfortunately, plating copper into blind vias places a limitation on how deep it can be drilled. Successful plating limits a blind via to a depth no greater than its diameter. Therefore, a 5-mil blind via can only route signals 5-mils deep. This restriction places a practical limitation on routing with blind vias. In most cases, laser-drilled blind via technology limits this routing method to the outer layers and the first buried layer.

Devices with pin pitches of less than 1mm that can be routed using layers one and two (or n and n-1, for the general case) may use a combination of through-hole drilled vias for the power pins and blind vias for signal routing. As a practical matter, this limits the total pin count to less than 100. Memory IC areas are the primary locations where this form of routing works well.

Calculating the effects of clearance hole arrays in power planes help ensure proper design of hole and pad stacks, resulting in higher-yield power planes and greater signal-quality preservation.

About the Author Lee W. Ritchey, B.S.E.E., owns Speeding Edge, a consulting firm specializing in high-speed design consulting and training. He has served on Printed Circuit Design's editorial review board and regularly contributes to a variety of publications. Ritchey has taught his High-Speed Design course to more than 3000 engineers and designers in several countries and is a regular lecturer at the PCB Design Conferences, the IPC conferences, and the UC Berkeley Engineering Extension.