Design Article
A guide to VHDL for embedded software developers: Part 1 – Essential commands
Peter Wilson
7/19/2011 1:05 AM EDT
This series of articles is designed to give concise and useful summary information on important language constructs and usage in VHDL – helpful and easy to use, but not necessarily complete.
It will introduce the key concepts in VHDL and the important syntax required for most VHDL designs, particularly with reference to Field Programmable Gate Arrays (FPGAs).
In most cases, the decision to use VHDL over other languages such as Verilog or SystemC, will have less to do with designer choice, and more to do with software availability and company decisions. Over the last decade or so, a ‘war of words’ has raged between the VHDL and Verilog communities about which is the best language, and in most cases it is completely pointless as the issue is more about design than syntax.
There are numerous differences in the detail between VHDL and Verilog, but the fundamental philosophical difference historically has been the design context of the two languages.
Verilog has come from a ‘bottom-up’ tradition and has been heavily used by the IC industry for cell-based design, whereas the VHDL language has been developed much more from a ‘topdown’ perspective.
Of course, these are generalizations and largely out of date in a modern context, but the result is clearly seen in the basic syntax and methods of the two languages. Without descending into a minute dissection of the differences between Verilog and VHDL one important advantage of VHDL is the ability to use multiple levels of model with different architectures.
This is not unique to VHDL, and in fact Verilog does have the concept of different behavior in a single ‘module’; however, it is explicitly defined in VHDL and is extremely useful in putting together practical multi-level designs in VHDL.
The division of a model into its interface part (the ‘entity’ in VHDL) and the behavior part (the ‘architecture’ in VHDL) is an incredibly practical approach for modeling multiple behavior for a single interface and makes model exchange and multiple implementations straightforward.
The remainder of the first part in this series will describe the key parts of VHDL, starting with the definition of a basic model structure using entities and architectures, discuss the important variable types, review the methods of encapsulating concur rent, sequential and hierarchical behavior and finally introduce the important fundamental data types required in VHDL.
Entity: model interface
Entity definition. The entity defines how a design element described in VHDL connects to other VHDL models and also defines the name of the model. The entity also allows the definition of any parameters that are to be passed into the model using hierarchy. The basic template for an entity is as follows:
entity
is
....
entity;
If the entity has the name ‘test’, then the entity template could be either:
entity test is
end entity test;
OR:
entity test is
end test;
Ports. The method of connecting entities together is using PORTS. These are defined in the entity using the following method:
port
(
...list of port declarations...
);
The port declaration defines the type of connection and direction where appropriate. For example, the port declaration for an input bit called in1 would be as follows:
in1 : in bit;
And if the model had two inputs (in1 and in2) of type bit and a single output (out1) of type bit, then the declaration of the ports would be as follows:
port (
in1, in2 : in bit;
out1 : out bit
);
As the connection points between entities are effectively the same as those inter-process connections, they are effectively signals and can be used as such within the VHDL of the model.
Generics. If the model has a parameter, then this is defined using generics. The general declaration of generics is shown below:
generic (
...list of generic declarations...
);
In the case of generics, the declaration is similar to that of a constant with the for m as shown below:
param1 : integer := 4;
Taking an example of a model that had two generics (gain (integer) and time_delay (time)), they could be defined in the entity as follows:
generic (
gain : integer := 4;
time_delay : time = 10 ns
);
Constants. It is also possible to include model specific constants in the entity using the standard declaration of constants method previously described, for example:
constant : rpullup : real := 1000.0;
Entity examples. To illustrate a complete entity, we can bring together the ports and generics examples previously and construct the complete entity for this example:
entity test is
port (
in1, in2 : in bit;
out1 : out bit
);
generic (
gain : integer := 4;
time_delay : time := 10 ns
);
constant : rpullup : real := 1000.0;
end entity test;
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simha_038
7/20/2011 7:18 PM EDT
Thank you for the informative article
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JB_DMAP
7/21/2011 3:07 PM EDT
It is always amazing to consider that VHDL or similar language are for software designers ! For it is clear that such language are only for hardware design and must be used by people with an hardware education. Do not confuse the tool (a language) with the objective ( an hardware item).
After all schematic capture was not a tool for cartoonists ...
This doesn't impact the global interest of such initiative, just let's be clear on the target.
James
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Bernard Cole
7/21/2011 3:42 PM EDT
I have never really understood the separation in the embedded developer community between hardware and software development, between hardware and software oriented languages. Since the emergence of VHDL, Verilog and later SystemC, HandelC even the hardware is software and developers there are concerned with the same issues: compilers, debuggers, verification, etc. And when the hardware languages were conceived they were not created out of thin air. Rather they were designed on what went before: VHDL roots are in Ada, Verilog's is in C and SystemC is based on C++.
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cpns
7/22/2011 4:25 AM EDT
I have to somewhat disagree with James; sounds like a hardware engineer jealously protecting what he considers to be his domain.
While implementing what might otherwise be discrete logic in an FPGA might be a hardware centric skill, that is to underestimate what an FPGA can do. They are also ideal a for accelerating algorithmic processing, and algorithms and algorithmic thinking is largely a software domain skill. My point is that you can use an FPGA to integrate hardware or to accelerate software, and the latter makes it of interest to software developers.
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JB_DMAP
7/22/2011 5:41 AM EDT
Dear all,
Of course we need to have some bridges between professional skills, and systems must be designed by people who understand what are the objectives and limitations of all the participants.
Definitively an hardware designer must be able to deal with language as C++ or SystemVerilog (it should be a part of his education).
But, to obtain a system we need some safety guys, some mechanical engineers, some architects, some thermal analysts (may be all of them are using C based language ?)...
I never though that I could replace a mechanical engineer only because Catia is a CAD tool and it could be possible to use it for a CAD professional as I expect to be ! Hardware and software are two faces of a system, with two different target (one can't compare the limitations of a real time OS to the limitations of a 90n FPGA).
I agree with the idea that there is a common vocabulary, but be careful, things are are not so simple it seems to be, although the methods are converging (we both talk about IP, functional coverage, formal methods ...)
By the way, I am not a jealous hardware engineer ! On contrary I spend a large part of my time to try to understand what is common and what is still different in our two words to make it progress. And I confirm that VHDL is a language dedicated to hardware design for hardware designers.
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deepak koranga
7/23/2011 7:44 AM EDT
I totally agree with James.I don't see any sense in seggragating any domain into two parts and then get it done by two different guys of whom one is somewhat out of the game.A hardware designer can easily understand what a piece of software code can do coz that's what he does manually.And let me tell you I'm not a frustrated hardware engineer but a EDA guy,just in case you think m being biased.:)
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cpns
7/23/2011 7:48 AM EDT
Well I am a software engineer (originally trained in electronics), and my experience of FPGA applications was for an image processing application involving lens distortion correction and feature detection and tracking. I cannot see how "hardware skills" necessarily equip you for for that, other than perhaps the boundary elements of the camera and microprocessor data/address bus interfaces, between those it is algorithmic data and signal processing which just happens to be implemented in hardware.
Admittedly this application was implemented in HandelC rather than VHDL, making it perhaps more familiar to software engineers, but that is rather the point - these tools allow software to be accelerated by implementing it directly in hardware - it remains a software skill.
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DKC
7/25/2011 12:37 PM EDT
VHDL, Verilog and SystemC are all pretty ugly and dysfunctional languages. Here's how to do the same thing in a cleaner way -
http://parallel.cc
The problem (as identified above) is that a logical separation of concerns (hardware vs software) caused an illogical separation in language development.
Thinking parallel is a skill needed for both hardware and software these days.
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Robotics Developer
7/25/2011 12:53 PM EDT
I can see valid points on both sides: hardware and software perspectives. I am an electrical engineer by profession and programmer by necessity. All too often I have seen software centric hardware designs that fail to reach the full speed (or reduced size) targets due to a lack of understanding of the hardware. I have also seen too many hardware based coders who create code that works but is convoluted, hard to fix, hard to maintain and generally not optimized. There are notable exceptions: that rare breed of engineer that does span both hardware and software! I have always been an advocate for the holistic systems solution approach, all too often we tend to focus on one aspect of the project to the detriment of the whole. Having a hardware degree and some experience coding (never enough!) has helped me to understand the system and taylor the approach for best results possible.
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perriejb
7/29/2011 3:39 AM EDT
I personnaly use a VHDL interpreter of C code to emulate a CPU communicating with what I want to test, i.e. the VHDL description of an FPGA.
When you think of it that way, you clearly see a difference between hardware and software.
A fundamental difference in hardware description is that you always keep in mind that the result of the synthesis of your "code" is a number of logic gates. Hence, you should avoid costly functions, such as multiplication and division (unless your logic device includes hardware implementation(s) of those functions).
You can use VHDL just like a programming language but you are shouldn't outside of simulation.
With the growing number of applications using parallel processing, I see the difference in the way of thinking your code/functional description shrinking, but to me the end purpose is still entirely different.
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