Keeping time on 40/100G networks with high-performance clocks

Networking service providers are significantly expanding their transmission network capacity to meet the burgeoning demand for bandwidth-intensive video and web-driven multimedia applications.

This application-focused demand is driving the migration from 10G to 40G and 100G high-speed optical links in both core and metro applications. Innovation is required on multiple fronts to deliver this capacity expansion at the lowest possible total cost of ownership (TCO) while maintaining network reliability and quality of service.

This network migration is being enabled by several new and exciting technologies such as coherent optics, which supports 40/100G transmission over existing or new fiber while eliminating the need for external bulk dispersion compensation modules.

Additional innovation is happening on the IC front, with both existing and startup semiconductor suppliers introducing 4 x 28 Gbps transmit and receive circuitry, pushing the speed and performance envelope.

Significant advances in clocking technology are required to keep pace with these technical breakthroughs and to deliver an overall hardware solution that meets 40/100G system requirements.

These clocking solutions must have sufficiently high performance to work in core transmission networks, but also must be flexible enough to work in higher density line cards intended for metro transport networks.

This combination of performance and flexibility is especially important for metro applications, since metro networks are expected to gradually migrate to a mix of 10G, 40G and 100G systems.

Challenges in 40/100G Optical Line Card Designs
There are four key challenges for clock generation in 40/100G optical line cards: frequency flexibility, clock jitter, cross-talk mitigation and phased-locked loop (PLL) integration.

Since 40/100G systems often must support a variety of protocols, including OTU3, OTU4, 10GbE and 100GbE, they also require multiple reference frequencies. Table 1 below shows typical frequencies required by these 40/100G systems.

Table 1. Common 40/100G Reference Clock Frequencies (Rounded)
Note that many of these rates are fractional frequencies that must be generated precisely. The clock device must have high input jitter tolerance and be able to synchronize to a jittered backplane reference, gapped clock input (for OTN asynchronous demapping applications) or to a local oscillator.

This requirement puts an additional restriction on the clock IC, since its PLL must often be able to support an input frequency that is non-integer related to its output frequency.

In addition, 40/100G clocking circuits may need to support custom frequencies required by field-programmable grid array (FPGA) solutions (e.g., 322.265625 MHz) or proprietary forward error correction (FEC) rates. To synthesize these frequencies and ensure a high degree of frequency accuracy, developers must use clock ICs supporting any-rate frequency synthesis.

Ultra-low clock jitter is of paramount importance given the stringent jitter requirements for 40/100G systems. An excessive level of clock jitter due to the intrinsic jitter of the line card’s frequency source, the line card jitter attenuating clock, FPGA/ASIC internal phase-locked loops (PLLs) or jitter due to board-level noise sources can make it difficult to meet system-level jitter requirements.

The 40/100G PHY contributes clock jitter as well. Its externally provided reference must be internally multiplied using a phase-locked loop (PLL) to a higher frequency to clock the transmitter at its given line rate.

Excessive jitter within this internal PLL or the rest of the timing path reduces the jitter margin of the overall design. Given these considerations, it is recommended that a jitter attenuating clock or local oscillator with ultra-low jitter be used (<0.4 ps rms or less) as the 40/100G PHY reference clock.

Power supply noise also impacts clock jitter. First, switch mode power supplies induce ripple, which can increase jitter on oscillators and clocks. Second, power supply noise can be induced by FPGAs ASICs and other devices.

FPGA/ASICs typically have multiple wide output banks that are simultaneously switched. This switching induces fluctuations on the power rail that ripple through the power plane and couple into adjacent devices including clock ICs.

Careful power plane design, noise isolation between ICs and increased power supply decoupling can mitigate power supply noise. However, cost, PCB layout and design constraints may limit the number of techniques available to hardware designers.

As a general rule of thumb, timing devices with extensive levels of internal linear voltage regulation are recommended in jitter-sensitive applications including 40/100G systems.