Picking the right MPSoC-based video architecture: Part 2

Monolithic CPUs
In addition to integrating various audio, video, and peripheral interface units, an emerging trend for multimedia SoCs is to muster enough processing power by utilizing multiple CPU cores.

In fact, quite a few of the currently available ICs already feature two CPUs. For a typical digital television, digital video set-top box, or DVD recorder system, Philips provides silicon that integrates a MIPS core and a TriMedia processor.

For a mobile handset baseband processor, Philips offers a combination of an ARM core or multiple ARM cores and an Adelante digital signal processor (DSP). The OMAP5910 SoC from TI also incorporates two CPU cores—a TMS320C55x digital signal processing core and a TI-enhanced ARM core.

For the PNX-8500, an architectural decision was made quite early in the design cycle to use the TM32 TriMedia core together with the standard MIPS32 reduced instruction set computing (RISC) core.

The choice was guided by the pre-existing (external) software stacks for the target application and Philips' own portfolio of processor cores with existing applications and standard compilers. The requirements on the RISC processor were high performance, capability to run popular embedded operating systems, and efficient control of infrastructure peripherals.

The VLIW processor, on the other hand, was required to have a very high performance and a multimedia-enhanced instruction set suitable for audio and video processing. This allows balancing of the system and distribution of tasks among the two CPUs.

The scheduling task in PNX-8500 is usually assigned to TM32—the CPU with the faster response time. Besides running all the audio decoding and processing functions, the TriMedia core also implements other nontrivial multimedia algorithms that are not supported directly by the hardware functional units.

The MIPS core, on the other hand, runs the operating system and, on top of it, the software application provided by the service provider. The application software deals with the accessibility of the service (conditional access) and the general control functions. All graphics-related functions are also handled by the MIPS processor.

Reconfigurable CPUs
Today's SoC architectures, as mentioned above, frequently exhibit only a few more or less powerful embedded processors that, depending on the application, might be RISC processors, VLIW cores, or DSPs. Recent trends in the embedded CPU IP market, however, show an increasing preference toward reconfigurable computing and, therefore, toward compile-time-configurable CPUs like Tensilica and ARC.

Extensible and configurable (tailored) processors offer many of the benefits of hardware accelerators (adding hardware for specific processing problems), while solving some of the problems associated with the design of hardware accelerators.

These reconfigurable CPUs are generated with software tools and customized with regard to not only the cache and memory size but also the number and kind of peripherals that need to be supported.

Another very helpful feature of these CPUs is the capability to add custom operations associated with hardware extensions such as lookup tables, x-y memories, add-compare-select units, and multiply-accumulate (MAC) units. These extensions make the CPUs very "DSP-like" and therefore well suited for baseband communication or media-processing tasks.

Reconfigurable hardware is believed by many to be an ideal candidate for use in SoCs because it offers a level of flexibility not available with more traditional circuitry.

Hardware reuse, for example, allows a single configurable architecture to implement many potential applications. Another flexibility offered is easy postfabrication modification that allows alterations in the target applications, bug fixes, and reuse of the SoC across multiple similar deployments to amortize design costs.

Reconfigurable logic, it has been argued, should, however, be used for the execution of tasks with moderate timing constraints, in order to benefit from the saving of silicon area owing to a more efficient utilization. It has also been argued that general CPUs are equipped with many functional units, thereby making it very difficult to obtain an optimal exploitation of the hardware resources.

With reconfigurable hardware, however, it is possible to "synthesize" the required units at the right time and to occupy only the chip area that is needed for the execution of the current task(s). Besides, dynamically reconfigurable systems also permit adaptive adjustments during run time.