Design Article
Video encoding with low-cost FPGAs for multi-channel H.264 surveillance
Suhel Dhanani, Senior Manager, Altera <br>and Vicenzo Liguori, Director, Ocean Logic Pty Ltd.
11/28/2008 4:15 PM EST
This article first lays out the architecture advantages of FPGAs for low-cost, yet high-performance video processing applications and then shows how these advantages translate into a real-world application in the rapidly expanding field of video surveillance systems.
Advantages of implementing video processing in low-cost FPGAs
Today's low-cost FPGAs feature a host of silicon features that enable high performance signal processing -- abundant multipliers, fast fabric performance, and large amounts of on-chip memory (see Table 1). This makes low-cost FPGAs an ideal platform to implement an emerging class of cost-sensitive, yet high quality image processing applications.
A good example is the family of Cyclone III FPGAs that are fabricated on advanced 65nm process technology and has abundant multiplier, memory, and logic resources that enable them to implement algorithmic-intensive applications such as video and image processing.
Table 1: Resources for Video and Image Processing in Cyclone III FPGAs
Power is an increasingly important consideration for many system designers. Built on the TSMC 65-nm low-power process technology, these FPGAs have additional silicon and software optimizations to offer an extremely low power consumption number.
Figure 1: The Typical Power Consumed by Cyclone III FPGAs for a Range of Density and Performance
While power consumption is very design dependant, the typical power consumption of a mid-range device (with over 50,000 logic elements) is lower than 1W. The static power consumption is less than 1/10th of this number (i.e. less than 100mW as shown in Figure 1).
This kind of low power consumption is critical in low-cost systems such as surveillance systems where cooling systems add to the cost of the system.
Abundant DSP resources on a low-cost, low-power fabric coupled with industry standard design flows allows high performance video applications to be implemented in a cost-effective manner on such FPGA platforms.
Next: FPGAs vs. DSPs
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aswakle
1/1/2009 8:10 AM EST
Figure 5 shows system encoding 1080p video at 20 FPS. I understand that the system implements data-parallelism whereby the two H264 encoder cores operate on different (successive) frames. However each core will require reference frame (generally the previous one) for ME and MC. If these cores are getting alternate frames, then their perception of reference frames is different and therefore the decoder may have an issue. This, of course, can be solved by using the "multiple reference picture" tool in H.264, whereby (n-2)th reference frame may be used by the encoder. So though the H.264 encoder core operates to use the successive frames, the decoder is informed that (N-2)nd reference frame is being used. And then there would be no issue. Would that be correct interpretation ?
Thanks,
Abhijeet Wakle
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