A low-cost solution for FPGA-based PCI Express implementation

With much higher densities, embedded intellectual property (IP) and higher I/O interconnects, FPGAs have evolved from being used only as glue logic into components that provide integral functionality in digital systems implementations. With the availability of high gate count, features, and support for various third-party EDA tools, designers can use a design flow similar to those used for ASIC devices to create systems employing FPGAs.

To facilitate implementing the PCI Express layers in low-cost and high-volume applications, low-cost FPGAs are available today with an external x1 PCI Express physical interface (PHY). These components are uniquely positioned to displace costly, high-risk solutions such as ASICs, and offer a cost-effective, more flexible and risk-free alternative (Fig 1).

1. Implementing PCI Express using the combination of a
low-cost FPGA and an external x1 PHY.

While some ASICs and ASSPs provide fully-integrated PCI Express solutions, there are numerous benefits to using FPGAs along with an external x1 PHY to implement PCI Express. New generations of products are being introduced to the market more rapidly than ever before; at the same time, windows of opportunity for market success are shrinking, causing manufacturers to search for new, flexible, low-cost, and fast development solutions.

The benefits of FPGA and x1 PHY low-cost PCI Express solutions
FPGAs with an x1 PHY provide rapid, low-cost innovation cycles and greater product differentiation that increase margins and assist in reaching the market quickly. Although ASSPs and ASICs provide a low-cost, fixed platform for PCI Express solutions, ASSPs reduce the ability to differentiate and to add the latest in-demand features, while ASICs are notorious for significantly jeopardizing on-time delivery and have inherently high development costs. Relying on ASICs or ASSPs for a design solution will get the competition to market first. Additionally, many ASSPs provide fixed functionality, not required for the design, and these devices are only available in more expensive, high-pin count packages.

Design costs utilizing an ASIC also continue to increase. In addition to the non-recurring engineering (NRE) and mask costs, development costs increase based on ASIC design complexity. Moreover, issues such as power, signal integrity, clock-tree synthesis and manufacturing defects can add significant risk and time-to-market delays. FPGAs offer a viable and highly competitive option to ASIC development by overcoming the risk of respins, high NRE costs and reducing time-to-market delays.

Designers must realize that not every application requires the full functionality offered by many PCI Express ASSPs. A single x1 PCI Express port implemented in a flexible low-cost FPGA interfacing to an external x1 transceiver can be the optimal solution in terms of feature set and cost.

With FPGAs, development efforts can be focused on implementing the features and enhancements critical to establishing a market leadership position. If ASICs or ASSPs are being used for standard – yet complex – functions, then use PLDs or structured ASICs for the latest high-value features. This methodology allows differentiating features to be added over a much longer time period with faster innovation than alternative silicon technologies.

Another key benefit of using an FPGA is integration. When FPGAs are already being used in a design and adding PCI Express functionality is desired, the FPGA and x1 PHY solution makes it simple to integrate the PCI Express. All one has to do is to add the PCI Express IP to the design and attach an x1 PHY to the existing FPGA. In this case, the PCI Express IP will contain the transaction layer, data link layer, MAC sub-layer, and the Physical Interface for PCI Express (PIPE) interface, thereby leaving designers free to focus on the unique, differentiating portions of the product.

Such a solution can also benefit from integrating other portions of the design, such as signal processing operations, external memory interfaces, and clock management into the FPGA. These functions can be implemented efficiently using the available embedded resources within FPGAs, including logic elements (LEs), multipliers, and phase-locked loops (PLLs). By using programmable logic to integrate various functions – including PCI Express – companies can reduce product costs and form factor, while at the same time increasing application performance.

FPGAs provide a programmable logic solution for a variety of PCI applications. With PCI Express rapidly succeeding PCI by providing higher performance, increased flexibility, and scalability for next-generation systems, it will be much cheaper and easier to make the transition by using an existing FPGA on board. In addition, users can maintain software compatibility with existing PCI applications.