Design Article

IMG1

I/O Design Flexibility with the FPGA Mezzanine Card

Raj Seelam, Xilinx Inc.

10/28/2009 1:49 PM EDT

Introduction

Facing a seemingly endless stream of new and evolving I/O standards, it is not surprising that today's embedded system designers continue to rely on FPGAs to perform the increasingly critical role of external I/O interface for their systems. FPGAs offer a large number of configurable I/Os that support a virtually limitless variety of highly complex I/O standards, given the right IP. The designer can also use an FPGA to perform in-stream data processing, even on protocols running at multi-gigabit signaling speeds and bandwidths.

FPGAs are highly adaptable to changes in I/O requirements. After reconfiguring an FPGA to implement a new protocol, little more is required than replacing the physical I/O components and connectors. Unless the I/O was implemented on a mezzanine module, this means changing the board's design. To avoid the costs and effort associated with a design change, designers have historically relied on the PCI Mezzanine Card (PMC) and Switched Mezzanine Card (XMC) standards. However, these standards were developed years ago for general purpose solutions such as single-board computers (SBCs) —not FPGAs. That changed in July of 2008 with the ratification and release of the VITA 57 FPGA Mezzanine Card (FMC) standard by the American National Standards Institute (ANSI).

Developed by a consortium of companies ranging from FPGA vendors to end users, the FMC standard was created to provide a standard mezzanine card form factor, connectors, and modular interface to an FPGA located on a base board (carrier card). Decoupling the I/O interfaces from the FPGA in this manner simplifies I/O interface module design while maximizing carrier card reuse. Unlike the PMC and XMC standards that use complex interfaces like PCI, PCI-X, PCIe, or Serial RapidIO to interface to the carrier card, the FMC standard requires only the core I/O transceiver circuitry that connects directly to the FPGA on the carrier card.

The resulting efficiencies translate to substantial benefits:

  • Data throughput: Individual signaling speeds up to 10 Gb/s are supported, with a potential overall bandwidth of 40 Gb/s between mezzanine and carrier card.
  • Latency: Elimination of protocol overhead removes latency and ensures deterministic data delivery.
  • Design simplicity: Expertise in protocol standards such as PCI, PCI Express, or Serial RapidIO are not required.
  • System overhead: Simplifying the system design reduces power consumption, IP core costs, engineering time, and material costs.
  • Design reuse: Whether using a custom in-house board design or a commercial off-the-shelf (COTS) mezzanine or carrier card, the FMC standard promotes the ability to retarget existing FPGA/carrier card designs to a new I/O. All that is required is swapping out the FMC module and slightly adjusting the FPGA design.
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