FPGA design starts are on the rise due to the lower startup costs and re-programmability that FPGA devices can provide. However, large, complex FPGA devices pose significant challenges to an FPGA project team. Only by following sound design flow practices can FPGA designers manage their projects effectively.

Modern design flows have FPGA synthesis positioned at the critically important junction between design creation and physical implementation. Because of this strategic placement in the design process, FPGA synthesis can provide significant leverage in achieving project cost, time and quality goals. In this article, we will discuss how FPGA synthesis tools can help designers achieve their goals efficiently and effectively.

Most development projects are driven by a familiar mantra: "faster, sooner, better." For FPGA designers, this translates into reducing time to market and project costs while meeting aggressive performance goals. Moreover, many projects require FPGA designers to follow strict certifiable process standards and at the same time manage project costs and delays.

But FPGA designers don't need to reinvent the wheel when developing a process. By borrowing proven practices from the ASIC design playbook they can achieve their project objectives without incurring huge NRE costs. In the discipline of ASIC design there is a strong emphasis on using the right methodology and tools. By adhering to this principle, engineering teams can achieve improved performance in every aspect of an FPGA project including technical results, schedule, productivity and cost. Recognizing this, FPGA designers are already turning to advanced methodologies, techniques and tools.

These modern FPGA design flows encourage efficient design practices including:

Figure 1 depicts a typical FPGA design flow. FPGA synthesis is the crucial step in which abstract high-level design ties in with the detailed physical design processes. Without investing excessive time and effort, designers can leverage the benefits of FPGA synthesis tools to achieve high-quality of results.

Figure 1. Synthesis is central to the modern hardware design flow (click on image to enlarge).

Vendor independence is not a tangible tool or a feature; it's more like a policy or unwritten rule that design teams adopt to help keep project costs down while maintaining flexibility.

The concept of vendor-independence is unique to FPGA designs, and it is where an FPGA project differs sharply from its ASIC counterpart. Some FPGA teams, when planning a large design project, consider only the early costs and effort. Unfortunately this locks them into a vendor-dependent design flow that may prove costly when it becomes necessary to modify the design or switch to a different device for any reason. A design that depends on one specific vendor's silicon and IP can't adapt readily when a different vendor's faster or cheaper components come to market a few months later. To avoid this pitfall it is vital to maintain vendor independence from the very beginning of a project.

No full-service EDA vendor supports just one FPGA provider's silicon platform. The EDA business model exists to serve designers working with any and all FPGA products, so the development tools provided by the EDA industry are innately vendor-independent. With these solutions, designers can use the same HDL code to target any suitable FPGA device on the market.

Taking the concept a step further, some FPGA synthesis solutions also make available vendor-independent IP blocks, both built-in and third party. This too spares FPGA designers from getting locked into a vendor-dependent flow.

ESL tools do not have a good picture of the design's structural and physical implementation. Instead, they rely on their own library of design elements for creating an HDL description. Accurately characterizing the area and timing numbers of these ESL design elements is an essential step toward creating high-quality HDL.

This too is a task the FPGA synthesis tool can perform. The characterization results delivered by the synthesis tool enable ESL tools to get a better grasp of the structural and physical design blocks and thereby generate an HDL description of correspondingly higher quality.

By using a variety of optimizations—some technology-independent and others technology-dependent—FPGA synthesis transforms a high-level design abstraction into a structural netlist. The quality of this netlist determines how effectively the place & route (P&R) tools can fit the design into the selected device environment while achieving the desired timing performance. Additionally, by supplementing the P&R tools with suitable optimizations in the physical synthesis realm, FPGA synthesis tools further improve the overall quality of the final design.

Most FPGA designs pass through at least a few iterations before achieving design closure. Engineers create and implement multiple design blocks and assemble these into a complete design. In a perfect world this would work the first time, but in reality designers almost always have to traverse back and forth through the design flow making functional changes, addressing QoR bottlenecks, or correcting problems.

When a high-level design methodology is used, it is important to visualize how the abstract ESL description is impacting the structural or physical design. Engineers need to be able to fine-tune and evolve the design at the system level in order to improve it at the physical level. In a disjointed tool flow this can be difficult.

In a well integrated flow, however, full-featured FPGA synthesis tools offer cross-probing capabilities across the entire flow as shown in Figure 2, from the ESL domain, through HDL, to post-place-and-route timing reports. A designer can examine a violation in the timing report, cross-probe to the offending line of code in the HDL code, and ultimately trace it back to the algorithmic description input to ESL synthesis. Such analysis capabilities enable quicker design debug.

Figure 2. Design flow with ESL and FPGA synthesis tools. Cross-probing enables outputs from later steps to be compared with inputs earlier in the flow (click on image to enlarge).

As FPGA designs become larger, verifying them becomes more time consuming. The easy way out for some designers is simply to put the design on a board and verify it in the lab. Unfortunately this approach is not as efficient as it might seem, since it introduces a host of new variables.

An FPGA synthesis tool that is integrated with formal verification tools offers an alternative to long, tedious simulations. Formal verification nominally provides 100% gate-level verification while avoiding the need to separately create vectors and run long simulations. The FPGA synthesis tool collaborates closely with the formal verification tool to selectively enable verifiable optimizations. This collaboration supports a smooth, integrated design verification flow and significantly improves engineering productivity.

Board-level design has a strong influence on the design of FPGAs that will be situated on the board. The choices made when assigning design ports to physical FPGA I/O pins impact the device's performance, often significantly. These same assignments also affect crucial board design parameters like electrical characteristics and the number of routing layers—and they influence both cost and performance at the board level.

Today's FPGA synthesis toolsets often include board-level I/O planning features that allow designers to create pin assignments suitable for board design. These assignments are then forward-annotated to the FPGA synthesis tool to drive advanced synthesis optimizations.

A smooth flow between the I/O planning tool and FPGA synthesis fosters both efficiency and quality. The tools encourage experimentation with diverse pin assignments while monitoring their effect on the system as a whole. Designers can then balance tradeoffs between board and FPGA to achieve optimum system performance.

As FPGA designs become larger and more complex, designers need to adopt advanced design methodologies and tools. FPGA Synthesis is central to these modern design flows. By enabling better design optimizations and by integrating with advanced design and verification tools, an FPGA synthesis tool can help designers reach their goals sooner, create designs that run faster, and deliver products of better quality.

About the author

Sanjay Thatte is Technical Marketing Manager for FPGA synthesis products at Mentor Graphics. Sanjay holds an M.S. from University of Washington and an MBA from San Jose State University. He has published several articles in the area of FPGA development. Sanjay has also created a fault-tolerant network structure and has coauthored its publication. His previous experience includes FPGA design planning and closure, design automation and design verification. He can be contacted at sanjay_thatte@mentor.com.