Easier cross-domain signal protection for mixed-signal SoCs

The complexity of system on chip (SoC) designs is increasing with the need for integrating more analog and digital circuits on the same chip. Mixed-signal designs require having different voltages to support every part on the chip. ICs with multiple separated power domains have signal lines that require crossing from one domain to another. Failures and damages may occur at these signal lines because they exist at the interface between different power domains. Designers must decide on the appropriate protection schemes and insert them at the crossing-domains interfaces. Up to now, several types of protection schemes have been used to avoid these failures.

Some of these solutions are used to overcome abnormal internal electrostatic discharge (ESD) damage by adding blocking resistors to the interface devices and fitting proper bidirectional diode connection cells between the separated power lines [1, 2]. One such interface protection scheme is performed using a resistor and a diode clamp to restrict the ESD current distribution and to clamp the overstress voltage across the gate oxide of the receiver's MOS transistors [3] (see Figure 1).

Another interface protection scheme is obtained by using a ground current trigger (GCT) NMOS transistor [4]. Under the cross-power-domain ESD stress, there is an induced voltage drop between GND1 and GND2. The GCT NMOS is turned on to clamp the overstress voltage across the gate oxide of the receiver's MOS transistors. Figure 2 illustrates this scheme.

Yet another scheme is implemented using gate-controlled PMOS (GC-PMOS) and gate-controlled NMOS (GC-NMOS) transistors with the ESD-transition detection function for interface circuits between separated power domains [1].