The complexity of system on chip (SoC) designs is increasing with the need for integrating more analog and digital circuits on the same chip. Mixed-signal designs require having different voltages to support every part on the chip. ICs with multiple separated power domains have signal lines that require crossing from one domain to another. Failures and damages may occur at these signal lines because they exist at the interface between different power domains. Designers must decide on the appropriate protection schemes and insert them at the crossing-domains interfaces. Up to now, several types of protection schemes have been used to avoid these failures.

Some of these solutions are used to overcome abnormal internal electrostatic discharge (ESD) damage by adding blocking resistors to the interface devices and fitting proper bidirectional diode connection cells between the separated power lines [1, 2]. One such interface protection scheme is performed using a resistor and a diode clamp to restrict the ESD current distribution and to clamp the overstress voltage across the gate oxide of the receiver's MOS transistors [3] (see Figure 1).

Another interface protection scheme is obtained by using a ground current trigger (GCT) NMOS transistor [4]. Under the cross-power-domain ESD stress, there is an induced voltage drop between GND1 and GND2. The GCT NMOS is turned on to clamp the overstress voltage across the gate oxide of the receiver's MOS transistors. Figure 2 illustrates this scheme.

Yet another scheme is implemented using gate-controlled PMOS (GC-PMOS) and gate-controlled NMOS (GC-NMOS) transistors with the ESD-transition detection function for interface circuits between separated power domains [1]. A further scheme uses three circuits: an ESD detector, a driver and a receiver. The ESD detector receives a supply voltage of a different power domain, detects an ESD stress and outputs control signals. The driver outputs a signal to a different power domain. The output signal is controlled to logical low by the control signal if an ESD stress is detected by the detector. The receiver receives a signal from the driver in a different power domain. The receiver is controlled by the control signal to protect it against the ESD stress. Both the driver and the receiver are located at the boundary between two power domains for driving and receiving a signal to and from a different power domain [5].

One more important interface for different domains is the voltage level shifter. It should be able to efficiently convert any voltage level to any other desired voltage level. This is especially important in complex ICs and SoCs. Figure 3 demonstrates the conventional voltage level shifter [6]. It involves two voltage supplies, one for the input domain (VDDI) and another one for the output domain (VDDO).

When the input signal in is at the VDDI value, inb is at GND value. Therefore, MN1 turns on and MN2 is off. Accordingly, outb signal is pulled to GND. This transition of outb signal turns on MP2 which pulls up the out signal to the VDDO value. When in is at GND, inb is at VDDI value. Consequently, MN1 is off and MN2 is on, which turns on MP1. MP1 pulls up the outb to the VDDO value.

There are other designs for level shifters that are more advanced than the basic conventional one shown here. For example, the single-supply voltage level shifter can handle both low-to-high and high-to-low voltage translations [6, 7]. The use of a single supply voltage reduces layout congestion by eliminating the need for routing both supply voltages. It also reduces the pin count at the interface of the modules working at different supply domains where level shifting is required. This reduces the overall complexity and cost of the system. Other level shifter designs target certain power, speed, or application specifications [8"14].

Automated checking of protection schemes

Multiple protection schemes are available for signals that cross different power domains. Every designer picks the protection schemes that fit the application. Because the absence of the protection schemes may lead to chip failure, they have to be verified in the design. However, with the growing complexity of mixed-signal chips, manually verifying protection schemes has become an impractical, time consuming, and inaccurate process that increases the risk of re-spin. In contrast, an automated programmable method reduces time and risk as well as improving accuracy when performing the checking operation. New programmable electrical rule checking (PERC), technology provides designers with an automated way to define rules for checking the desired interface protection schemes and how the violations are reported. The technology allows designers to customize the rules and reporting criteria, requiring two inputs: a design netlist and the rules deck, to do this. The design netlist can be a schematic netlist or an extracted netlist from a chip-layout. The latter can be generated using a layout versus schematic tool. The PERC technology then generates two outputs: an ASCII report and a database. The latter is used to support the visualization of the results and enable cross-probing with the design schematic or chip-layout. Figure 4 depicts a PERC verification flow.

Case study

The case study used here is an example of checking for protection of signal crossing different domains using the conventional voltage level shifter (Figure 3). In this situation, first the designer implemented the PERC rules needed to check this scheme. Subsequently, the designer used the PERC technology on his design to verify it. The signal lines that miss the protection scheme were reported as violations. Figure 5 illustrates the results.

Click on image to enlarge.

From this figure, you can see signal line out1 is crossing from VDDL domain to VDDH domain without the conventional voltage level shifter protection. The reporting style was defined by the designer using text messages and hyperlinks to simplify the results to aid in debugging the root of the problem.

Conclusion

Signals crossing different domains need to be protected, and multiple protection schemes can be used. The complexity of SoCs is increasing, but designers can now verify the existence of the protection schemes automatically by using a programmable and customizable solution to avoid wasted time and money. PERC technology supports successful and efficient circuit reliability checking by providing a flexible approach for coding protection schemes and detecting violations. References

[1] Shih-Hung Chen, Ming-Dou Ker, and Hsiang-Pin Hung, "Active ESD Protection Design for Interface Circuits Between Separated Power Domains Against Cross-Power-Domain ESD Stresses," IEEE Transactions on Device and Materials Reliability, volume 8, issue3, Sept. 2008, pp. 549"560.

[2] Hsiang-Pin Hung, Ming-Dou Ker, Shih-Hung Chen, and Che-Hao Chuang, "Abnormal ESD Damages Occur in Interface Circuits between Different Power Domains in ND-Mode MM ESD Stress," 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits, July 2006, pp. 163"166.

[3] E.R. Worley, "Distributed Gate ESD network Architecture for Inter-Power Domain Signals," in Proc. EOS/ESD Symposium, Sept. 2004, pp. 1"10.

[4] Mototsugu Okushima, "ESD Protection Design for Mixed-Power Domains in 90nm CMOS with New Efficient Power Clamp and GND Current Trigger (GCT) Technique," in Proc. EOS/ESD Symposium, Sept. 2006, pp. 205"213.

[5] Nobutaka Kitagawa, Hirotomo Ishii, Junichiro Watanabe, and Masazumi Shiochi, "An Active ESD Protection Technique for the Power Domain Boundary in a Deep Submicron IC," in Proc. EOS/ESD Symposium, Sept. 2006, pp. 19"204.

[6] R. Garg, G. Mallarapu, and S.P. Khatri, "Single-Supply True Voltage Level Shifter," in Proc. DATE, March 2008, pp. 979"984.

[7] Q.A. Khan, S.K. Wadhwa, and K. Misri, "A Single Supply Level Shifter for Multi-Voltage Systems," 19th International Conference on VLSI Design, Jan. 2006.

[8] J. F. da Rocha, M. B. dos Santos, J. M. Dores Costa, and F. A. Lima, "Level Shifters and DCVSL for a Low-Voltage CMOS 4.2-V Buck Converter," IEEE Transactions on Industrial Electronics, volume 55, issue 9, Sept. 2008, pp. 3315"3323.

[9] N.B. Zain Ali, M. Zwolinski, and B.M. Al-Hashimi, "Testing of Level Shifters in Multiple Voltage Designs," 14th IEEE International Conference on Electronics, Circuits, and Systems, Dec. 2007, pp. 435"438. [10] M. Rossberg, B. Vogler, and R. Herzer, "600V SOI Gate Driver IC with Advanced Level Shifter Concepts for Medium and High Power Applications," European Conference on Power Electronics and Applications, Sept. 2007, pp. 1"8.

[11] J. Rocha, M. Santos, J.M.D. Costa, and F. Lima, "High Voltage Tolerant Level Shifters and DCVSL in Standard Low Voltage CMOS Technologies," IEEE International Symposium on Industrial Electronics, June 2007, pp. 775"780.

[12] Bert Serneels, Michiel Steyaert, and Wim Dehaene, "A High Speed, Low Voltage to High Voltage Level Shifter in Standard 1.2V 0.13 ¼m CMOS," 13th IEEE International Conference on Electronics, Circuits, and Systems, Dec. 2006, pp. 668"671.

[13] Byung Seong Bae, Jae Won Choi, Jae Hwan Oh, and Jin Jang, "Level Shifter Embedded in Drive Circuits with Amorphous Silicon TFTs," IEEE Transactions on Electron Devices, volume 53, issue 3, March 2006, pp. 494"498. [14] Bo Zhang, Liping Liang, and Xingjun Wang, "A New Level Shifter with Low Power in Multi-Voltage System," 8th International Conference on Solid-State and Integrated Circuit Technology, 2006, pp. 1857"1859.

About the Author

Dina Medhat is a technical marketing engineer for Calibre Design Solutions at Mentor Graphics. She holds an MSc in electronic design automation from Ain Shames University, Cairo, Egypt.