A Current Sensing Tutorial—Part IV: Layout and Troubleshooting Guidelines

Input Bias Current

Before introducing the effects of PCB layout on accuracy, the input bias current specification (Ib) must be understood. Input bias current is defined as "The average of the currents into the two input terminals with the output at the specified level."[1] Ideally this specification is 0A, but process variations and design constraints cause this to be a non-zero value. With respect to current sensing, this specification has two implications. First, Ib becomes important when trying to accurately sense ‘small’ currents. For example, attempting to measure a system load current of 100uA with a device whose Ib=35uA would yield great uncertainty in the measurement. Secondly, poor matching between the two input signal currents (or input offset current, Ios) could induce and/or exacerbate a differential voltage at the inputs of the device. The latter will be discussed in this article.

Theory

Part 3 in this series discussed accuracy with respect to device specifications such as Vos, CMRR, and PSRR. It also presented and discussed a table similar to the one depicted below. The differences include the addition of two rows and one column. Rows for Ib and offset voltage due to PCB layout (Vos-pcb) have been added. A column designating whether or not each error source is within the control of the designer was also added.

Notice that the only error source that is within the control of the designer is Vos-pcb. This is because all of the other error sources are device specifications, which cannot be realistically controlled outside of selecting a different device with improved specifications. Vos-pcb can be minimized through proper PCB layout. Unfortunately it is often the case where the appropriate device is selected, but the PCB layout causes an unacceptable amount of additional error.

Example Design

In order to observe the effects of PCB layout on a current sensing solution, let’s create an example design. Suppose the solution requirements are as follows:

* Common-mode voltage (Vcm): 70V

* Available supply for differential amplifier (Vs): 5V

* Load current range: 5A<Iload<10A

* Unidirectional

* High accuracy

Since the common-mode voltage is considerable and greater than the supply voltage available for the differential amplifier, a current shunt monitor (CSM) should be the device of choice. The INA282 (Gain=50V/V) CSM meets the above requirements for it can accommodate common-mode voltages up to 80V, operate on supply voltages from 2.7V to 18V, can be used in either bidirectional or unidirectional applications, and has an input offset voltage (Vos) specification of only 70µV(max).

In order to properly size the shunt resistor we must examine the input and output specifications of the device. With a supply voltage of 5V, the output of the INA282 can swing from 40mV to 4.6V. Dividing the output range by the gain of the device (50V/V) yields the input range. This equates to an input voltage range from 0.8mV to 92mV.

Given our load current of 5A (Iload-min) to 10A (Iload-max), the shunt resistor must be smaller than 9.2mΩ (92mV/Iload-max) and larger than 0.16mΩ (0.8mV/Iload-min). If the power dissipation of the shunt resistor is tolerable, it is recommended to use a larger valued shunt resistor for accuracy purposes. Therefore, we will select a shunt resistor of 8mΩ.

Figure 1 depicts the TINA-TI simulation circuit used to verify the design. Figure 2 shows the output of the INA282 vs. load current.

Now that we have a working example, let’s look at the effects PCB layout can have on the accuracy of this solution. Figure 3 depicts the same circuit as Figure 1, but with the addition of the parasitic resistances (Rps, Rpp, and Rpn). It also differentiates between the shunt voltage (Vshunt) and the sense voltage (Vsense). Vsense is defined as the differential voltage at the input pins of the device. Ideally, Vshunt=Vsense. Due to PCB parasitics, however, this will not be the case. Therefore, V’sense represents the non-ideal sense voltage.

Similar to our previous accuracy discussion, the error due to the PCB layout can be defined as shown in Equation 1.

where Vos-pcb is defined as:

From Figure 3 we can also derive an equation for V’sense in terms of the parasitic resistances and bias currents.

By Kirchoff’s current law (KCL):

By Kirchoff’s voltage law (KVL) and the passive sign convention:

Solving for V’sense yields:

Equation 6 shows us that any parasitic resistance in series with the shunt resistor, Rps, induces an error that will be observed at the output of the current sensing device. It also shows that parasitic resistances in series with the inputs of the current sensing device, Rpp and Rpn, may or may not induce an error. If Ibp*Rpp=Ibn*Rpn, no error will be observed. Any deviation from this relationship will induce error.

Rpn and Rpp errors

While the system designer cannot control the input bias currents, they can attempt to match the resistances of the input traces. Failure to balance the input trace resistances will most likely be perceived as an error.

For example, one-ounce copper input traces of 350mils in length and 10mils wide have an impedance of approximately 17mΩ. Table 2 summarizes the effects of such input traces on the circuit from Figure 3 with a load current of 5A.

Using the ideal shunt voltage value of 40mV, we calculate the error due to balanced input traces using Equations 1, 2 as follows:

Failure to balance the input traces, however, can yield a more significant error. Let’s repeat the calculations but use imbalanced traces. Let’s assume one of the traces is 275mils in length while the other is 350mils long. The results of the simulation are shown in Table 3.

We see a 35.7 percent increase in error with a 75mil imbalance. Two additional topics to mention here include temperature variations and vias. These errors can increase further due to temperature fluctuations. Additionally, placing the current sensing device and the shunt resistor on opposite sides of the board necessitate the use of vias. Vias can have significant parasitic impedances which can vary greatly with manufacturing.