Design Article
Introduction to USB—Part IV
Christian Legare, Micrium
1/16/2013 1:58 PM EST
USB DATA FLOW MODEL
Figure 1-25 shows a graphical representation of the data flow model.
F1-25(2) USB pipes allow associations between the host application and the device’s endpoints. Host applications send and receive data through USB pipes.
F1-25(3) The host controller is responsible for the transmission, reception, packing and unpacking of data over the bus.
F1-25(4) Data is transmitted via the physical media.
F1-25(5) The device controller is responsible for the transmission, reception, packing and unpacking of data over the bus. The USB controller informs the USB device software layer about several events such as bus events and transfer events.
F1-25(6) The device software layer responds to the standard request, and implements one or more USB functions as specified in the USB class document.
TRANSFER COMPLETION
The notion of transfer completion is only relevant for control, bulk and interrupt transfers as isochronous transfers occur continuously and periodically by nature. In general, control, bulk and interrupt endpoints must transmit data payload sizes that are less than or equal to the endpoint’s maximum data payload size. When a transfer’s data payload is greater than the maximum data payload size, the transfer is split into several transactions whose payload is maximum-sized except the last transaction, which contains the remaining data. A transfer is deemed complete when:
- The endpoint transfers exactly the amount of data expected.
- The endpoint transfers a short packet, that is a packet with a payload size less than the maximum.
- The endpoint transfers a zero-length packet.
DATA PACKET SIZE, TYPES, AND SPEED
Endpoints have several attributes in addition to their type, one of them being the maximum quantity of data that the endpoint can provide or consume in a single transaction.
A single transfer can involve less than the maximum quantity of data an endpoint can handle.
NEXT: Transactions, Transfers, and Frames
µC/USB Device: Universal Serial Bus Device Stack for the Renesas RX63N, Chapter 2, by Christian Legare, is excerpted with permission. The text is available at Micrium.
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N6DJL
1/17/2013 7:52 AM EST
This description is the most clear and concise that I have ever seen! I wish I had seen this years ago.
Thanks.
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cmathas
1/17/2013 2:55 PM EST
Ah, better late! There will be at least 2-3 more segments posted. Stay tuned!
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Colli
1/21/2013 5:13 AM EST
no 0000 packet ID?
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DonkeyHotay
1/22/2013 11:39 AM EST
packet ID 1100 is both PRE and ERR ?
I'm confused!
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reanimator
1/23/2013 5:37 AM EST
-- packet ID 1100 is both PRE and ERR ?
Good question
Here what I have found regarding this:
* PRE Is issued to hubs by the host to indicate that the
next packet is low speed.
* ERR: Returned by a hub to report an error in a split
transaction. (HS Only)
Source: [http://www.cypress.com/?docID=33237]
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